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e986211827
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
139 lines
4.9 KiB
C
139 lines
4.9 KiB
C
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Shunli Wang <shunli.wang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt2701-clk.h>
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static const struct mtk_gate_regs bdp0_cg_regs = {
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.set_ofs = 0x0104,
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.clr_ofs = 0x0108,
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.sta_ofs = 0x0100,
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};
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static const struct mtk_gate_regs bdp1_cg_regs = {
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.set_ofs = 0x0114,
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.clr_ofs = 0x0118,
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.sta_ofs = 0x0110,
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};
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#define GATE_BDP0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &bdp0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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#define GATE_BDP1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &bdp1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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static const struct mtk_gate bdp_clks[] = {
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GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
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GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
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GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
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GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
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GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
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GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
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GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
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GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
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GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
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GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
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GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
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GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
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GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
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GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
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GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
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GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
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GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
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GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
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GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
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GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
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GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
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GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
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GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
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GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
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GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
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GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
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GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
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GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
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GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
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GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
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GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
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GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
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GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
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GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
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GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
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GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
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GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
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GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
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GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
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GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
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GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
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GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
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GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
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GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
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GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
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GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
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GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
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GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
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GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
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};
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static const struct of_device_id of_match_clk_mt2701_bdp[] = {
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{ .compatible = "mediatek,mt2701-bdpsys", },
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{}
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};
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static int clk_mt2701_bdp_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
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mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return r;
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}
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static struct platform_driver clk_mt2701_bdp_drv = {
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.probe = clk_mt2701_bdp_probe,
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.driver = {
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.name = "clk-mt2701-bdp",
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.of_match_table = of_match_clk_mt2701_bdp,
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},
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};
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builtin_platform_driver(clk_mt2701_bdp_drv);
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