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84dbf97808
* Prepare to enable SMP on R-Car E2 (r8a7794). Geert Uytterhoeven says: "The main hurdle here is that R-Car Gen2 boot loaders do not initialize the arch_timer CNTVOFF register, which thus needs workarounds on Linux. - The first patch adds a definition for MON_MODE, as suggested by Marc Zyngier, - The second patch makes sure CNTVOFF is initialized for boot and secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done for the boot Cortex-A7 CPU core. Without this, the ARM arch timer does not work on secondary CPU cores." A follow-up patch to enable SMP in DT on R-Car E2 (r8a7794) is currently deferred unto v4.16 as it depends on the above. * Enable low-level debugging support for RZ/G1E (r8a7745). Fabrizio Castro says, "RZ/G1E uses SCIF4 for the debug console." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZyLU1AAoJENfPZGlqN0++MsIQAIgwPv0a1uChS3rpMSsm1j9Z kh5Xyu+JHSLT9XrX7KvH0dY7Or4y+36neZsHUWzb7JZm4BpKfuJ14jiO/diEh9qC UFdSgrsm4ARMnVGo/SaqwuYFSJZlE91EdN8G+NQFi9UB/BXJzsJYRaqif3IuOaVw Bc4NGrNLu6k5Y2MWYdfoeIOwvSRRy16Tts4YESyBESv97JR+7QjObC3LRMarS8XA Qc/CRXiFxWlbYVuquoSo1quZW43u1mMxXGCYI9EX+uGHlLrd28Vjh0Rq2ZCs84tc tVswAkLbnZVIlvJO9ovXW1y1zYw1jA7KrLLgJSff68fC6lXfV8RMgwTU1f3N2K6w 9U4PEjdPxyagGnUhX5bjOFGZC079j5xauOMwDWGEM4Jt1wsPZUPO83G9G19dbmeA zECBMqWqeXTnR4oRpolF0A53wqbIqe+GuQ8mYnZQCEvwx6mjuhPk4ae3AwpcvcQP Zlt1OSe0c9c/IRBeNK4q1qXXYG24AoBfzQ4L0EALKU1ESg3RYKMdH6WWcbezmp+q N4idtVnl+NowBtuvBzpao7EdYlGTHolsUJfYhwXxdKKWnxFzuOQapHC/PR5P6jnJ yzrc/rhWkWAShobzhYz+y21U93Aok96Fh3XqI0Lw+IRAN/l9kXKaQdlQJN+gfJ/4 yhudaIIlPCU6BGrbi0gK =4lQB -----END PGP SIGNATURE----- Merge tag 'renesas-soc-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Renesas ARM Based SoC Updates for v4.15" from Simon Horman: * Prepare to enable SMP on R-Car E2 (r8a7794). Geert Uytterhoeven says: "The main hurdle here is that R-Car Gen2 boot loaders do not initialize the arch_timer CNTVOFF register, which thus needs workarounds on Linux. - The first patch adds a definition for MON_MODE, as suggested by Marc Zyngier, - The second patch makes sure CNTVOFF is initialized for boot and secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done for the boot Cortex-A7 CPU core. Without this, the ARM arch timer does not work on secondary CPU cores." A follow-up patch to enable SMP in DT on R-Car E2 (r8a7794) is currently deferred unto v4.16 as it depends on the above. * Enable low-level debugging support for RZ/G1E (r8a7745). Fabrizio Castro says, "RZ/G1E uses SCIF4 for the debug console." * tag 'renesas-soc-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15 ARM: Add definition for monitor mode ARM: debug-ll: Add support for r8a7745 |
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