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d0f11d14b0
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/*
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* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*
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* Based on ccu-sun8i-h3.h, which is:
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* Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_SUN8I_H3_H_
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#define _CCU_SUN8I_H3_H_
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#include <dt-bindings/clock/sun8i-v3s-ccu.h>
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#include <dt-bindings/reset/sun8i-v3s-ccu.h>
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#define CLK_PLL_CPU 0
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#define CLK_PLL_AUDIO_BASE 1
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_AUDIO_2X 3
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#define CLK_PLL_AUDIO_4X 4
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#define CLK_PLL_AUDIO_8X 5
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#define CLK_PLL_VIDEO 6
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#define CLK_PLL_VE 7
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#define CLK_PLL_DDR 8
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#define CLK_PLL_PERIPH0 9
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#define CLK_PLL_PERIPH0_2X 10
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#define CLK_PLL_ISP 11
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#define CLK_PLL_PERIPH1 12
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/* Reserve one number for not implemented and not used PLL_DDR1 */
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/* The CPU clock is exported */
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#define CLK_AXI 15
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#define CLK_AHB1 16
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#define CLK_APB1 17
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#define CLK_APB2 18
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#define CLK_AHB2 19
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/* All the bus gates are exported */
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/* The first bunch of module clocks are exported */
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#define CLK_DRAM 58
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_MBUS 72
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/* And the GPU module clock is exported */
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#define CLK_NUMBER (CLK_MIPI_CSI + 1)
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#endif /* _CCU_SUN8I_H3_H_ */
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