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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
310 lines
7.4 KiB
C
310 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/* NXP PCF50633 Power Management Unit (PMU) driver
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*
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* (C) 2006-2008 by Openmoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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* Balaji Rao <balajirrao@openmoko.org>
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* All rights reserved.
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include <linux/mfd/pcf50633/core.h>
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#include <linux/mfd/pcf50633/mbc.h>
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int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
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void (*handler) (int, void *), void *data)
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{
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if (irq < 0 || irq >= PCF50633_NUM_IRQ || !handler)
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return -EINVAL;
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if (WARN_ON(pcf->irq_handler[irq].handler))
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return -EBUSY;
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mutex_lock(&pcf->lock);
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pcf->irq_handler[irq].handler = handler;
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pcf->irq_handler[irq].data = data;
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mutex_unlock(&pcf->lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pcf50633_register_irq);
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int pcf50633_free_irq(struct pcf50633 *pcf, int irq)
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{
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if (irq < 0 || irq >= PCF50633_NUM_IRQ)
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return -EINVAL;
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mutex_lock(&pcf->lock);
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pcf->irq_handler[irq].handler = NULL;
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mutex_unlock(&pcf->lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pcf50633_free_irq);
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static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask)
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{
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u8 reg, bit;
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int idx;
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idx = irq >> 3;
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reg = PCF50633_REG_INT1M + idx;
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bit = 1 << (irq & 0x07);
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pcf50633_reg_set_bit_mask(pcf, reg, bit, mask ? bit : 0);
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mutex_lock(&pcf->lock);
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if (mask)
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pcf->mask_regs[idx] |= bit;
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else
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pcf->mask_regs[idx] &= ~bit;
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mutex_unlock(&pcf->lock);
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return 0;
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}
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int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
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{
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dev_dbg(pcf->dev, "Masking IRQ %d\n", irq);
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return __pcf50633_irq_mask_set(pcf, irq, 1);
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}
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EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
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int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
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{
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dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq);
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return __pcf50633_irq_mask_set(pcf, irq, 0);
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}
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EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
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int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
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{
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u8 reg, bits;
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reg = irq >> 3;
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bits = 1 << (irq & 0x07);
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return pcf->mask_regs[reg] & bits;
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}
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EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
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static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq)
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{
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if (pcf->irq_handler[irq].handler)
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pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data);
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}
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/* Maximum amount of time ONKEY is held before emergency action is taken */
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#define PCF50633_ONKEY1S_TIMEOUT 8
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static irqreturn_t pcf50633_irq(int irq, void *data)
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{
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struct pcf50633 *pcf = data;
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int ret, i, j;
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u8 pcf_int[5], chgstat;
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/* Read the 5 INT regs in one transaction */
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ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
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ARRAY_SIZE(pcf_int), pcf_int);
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if (ret != ARRAY_SIZE(pcf_int)) {
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dev_err(pcf->dev, "Error reading INT registers\n");
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/*
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* If this doesn't ACK the interrupt to the chip, we'll be
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* called once again as we're level triggered.
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*/
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goto out;
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}
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/* defeat 8s death from lowsys on A5 */
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pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04);
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/* We immediately read the usb and adapter status. We thus make sure
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* only of USBINS/USBREM IRQ handlers are called */
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if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
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chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
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if (chgstat & (0x3 << 4))
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pcf_int[0] &= ~PCF50633_INT1_USBREM;
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else
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pcf_int[0] &= ~PCF50633_INT1_USBINS;
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}
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/* Make sure only one of ADPINS or ADPREM is set */
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if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
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chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
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if (chgstat & (0x3 << 4))
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pcf_int[0] &= ~PCF50633_INT1_ADPREM;
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else
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pcf_int[0] &= ~PCF50633_INT1_ADPINS;
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}
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dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
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"INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
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pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
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/* Some revisions of the chip don't have a 8s standby mode on
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* ONKEY1S press. We try to manually do it in such cases. */
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if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
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dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
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pcf->onkey1s_held);
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if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
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if (pcf->pdata->force_shutdown)
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pcf->pdata->force_shutdown(pcf);
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}
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if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
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dev_info(pcf->dev, "ONKEY1S held\n");
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pcf->onkey1s_held = 1 ;
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/* Unmask IRQ_SECOND */
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pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
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PCF50633_INT1_SECOND);
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/* Unmask IRQ_ONKEYR */
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pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
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PCF50633_INT2_ONKEYR);
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}
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if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
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pcf->onkey1s_held = 0;
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/* Mask SECOND and ONKEYR interrupts */
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if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
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pcf50633_reg_set_bit_mask(pcf,
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PCF50633_REG_INT1M,
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PCF50633_INT1_SECOND,
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PCF50633_INT1_SECOND);
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if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
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pcf50633_reg_set_bit_mask(pcf,
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PCF50633_REG_INT2M,
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PCF50633_INT2_ONKEYR,
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PCF50633_INT2_ONKEYR);
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}
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/* Have we just resumed ? */
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if (pcf->is_suspended) {
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pcf->is_suspended = 0;
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/* Set the resume reason filtering out non resumers */
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for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
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pcf->resume_reason[i] = pcf_int[i] &
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pcf->pdata->resumers[i];
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/* Make sure we don't pass on any ONKEY events to
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* userspace now */
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pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
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}
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for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
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/* Unset masked interrupts */
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pcf_int[i] &= ~pcf->mask_regs[i];
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for (j = 0; j < 8 ; j++)
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if (pcf_int[i] & (1 << j))
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pcf50633_irq_call_handler(pcf, (i * 8) + j);
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}
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out:
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_PM
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int pcf50633_irq_suspend(struct pcf50633 *pcf)
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{
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int ret;
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int i;
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u8 res[5];
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/* Make sure our interrupt handlers are not called
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* henceforth */
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disable_irq(pcf->irq);
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/* Save the masks */
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ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
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ARRAY_SIZE(pcf->suspend_irq_masks),
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pcf->suspend_irq_masks);
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if (ret < 0) {
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dev_err(pcf->dev, "error saving irq masks\n");
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goto out;
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}
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/* Write wakeup irq masks */
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for (i = 0; i < ARRAY_SIZE(res); i++)
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res[i] = ~pcf->pdata->resumers[i];
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ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
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ARRAY_SIZE(res), &res[0]);
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if (ret < 0) {
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dev_err(pcf->dev, "error writing wakeup irq masks\n");
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goto out;
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}
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pcf->is_suspended = 1;
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out:
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return ret;
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}
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int pcf50633_irq_resume(struct pcf50633 *pcf)
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{
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int ret;
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/* Write the saved mask registers */
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ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M,
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ARRAY_SIZE(pcf->suspend_irq_masks),
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pcf->suspend_irq_masks);
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if (ret < 0)
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dev_err(pcf->dev, "Error restoring saved suspend masks\n");
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enable_irq(pcf->irq);
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return ret;
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}
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#endif
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int pcf50633_irq_init(struct pcf50633 *pcf, int irq)
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{
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int ret;
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pcf->irq = irq;
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/* Enable all interrupts except RTC SECOND */
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pcf->mask_regs[0] = 0x80;
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pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]);
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pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
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pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
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pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
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pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
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ret = request_threaded_irq(irq, NULL, pcf50633_irq,
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IRQF_TRIGGER_LOW | IRQF_ONESHOT,
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"pcf50633", pcf);
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if (ret)
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dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
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if (enable_irq_wake(irq) < 0)
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dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
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"in this hardware revision", irq);
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return ret;
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}
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void pcf50633_irq_free(struct pcf50633 *pcf)
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{
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free_irq(pcf->irq, pcf);
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}
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