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https://github.com/edk2-porting/linux-next.git
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fea966f756
The SH instruction set has several instructions which accept an 8 bit immediate operand. For logical instructions this operand is zero extended, for arithmetic instructions the operand is sign extended. After adding an option to the assembler to check this, it was found that several pieces of assembly code were assuming this behaviour, and in one case getting it wrong. So this patch explicitly sign extends any immediate operands, which makes it obvious what is happening, and fixes the one case which got it wrong. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
123 lines
1.8 KiB
ArmAsm
123 lines
1.8 KiB
ArmAsm
! entry.S macro define
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.macro cli
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stc sr, r0
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or #0xf0, r0
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ldc r0, sr
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.endm
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.macro sti
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mov #0xfffffff0, r11
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extu.b r11, r11
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not r11, r11
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stc sr, r10
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and r11, r10
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#ifdef CONFIG_CPU_HAS_SR_RB
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stc k_g_imask, r11
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or r11, r10
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#endif
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ldc r10, sr
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.endm
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.macro get_current_thread_info, ti, tmp
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#ifdef CONFIG_CPU_HAS_SR_RB
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stc r7_bank, \ti
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#else
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mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
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shll8 \tmp
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shll2 \tmp
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mov r15, \ti
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and \tmp, \ti
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#endif
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.endm
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#ifdef CONFIG_TRACE_IRQFLAGS
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.macro TRACE_IRQS_ON
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mov.l r0, @-r15
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mov.l r1, @-r15
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mov.l r2, @-r15
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mov.l r3, @-r15
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mov.l r4, @-r15
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mov.l r5, @-r15
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mov.l r6, @-r15
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mov.l r7, @-r15
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mov.l 7834f, r0
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jsr @r0
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nop
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mov.l @r15+, r7
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mov.l @r15+, r6
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mov.l @r15+, r5
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mov.l @r15+, r4
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mov.l @r15+, r3
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mov.l @r15+, r2
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mov.l @r15+, r1
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mov.l @r15+, r0
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mov.l 7834f, r0
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bra 7835f
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nop
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.balign 4
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7834: .long trace_hardirqs_on
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7835:
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.endm
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.macro TRACE_IRQS_OFF
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mov.l r0, @-r15
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mov.l r1, @-r15
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mov.l r2, @-r15
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mov.l r3, @-r15
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mov.l r4, @-r15
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mov.l r5, @-r15
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mov.l r6, @-r15
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mov.l r7, @-r15
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mov.l 7834f, r0
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jsr @r0
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nop
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mov.l @r15+, r7
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mov.l @r15+, r6
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mov.l @r15+, r5
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mov.l @r15+, r4
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mov.l @r15+, r3
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mov.l @r15+, r2
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mov.l @r15+, r1
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mov.l @r15+, r0
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mov.l 7834f, r0
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bra 7835f
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nop
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.balign 4
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7834: .long trace_hardirqs_off
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7835:
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.endm
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#else
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.macro TRACE_IRQS_ON
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.endm
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.macro TRACE_IRQS_OFF
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.endm
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#endif
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#if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
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# define PREF(x) pref @x
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#else
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# define PREF(x) nop
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#endif
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/*
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* Macro for use within assembly. Because the DWARF unwinder
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* needs to use the frame register to unwind the stack, we
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* need to setup r14 with the value of the stack pointer as
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* the return address is usually on the stack somewhere.
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*/
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.macro setup_frame_reg
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#ifdef CONFIG_DWARF_UNWINDER
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mov r15, r14
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#endif
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.endm
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