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138f4c359d
Channel switching is problematic for some dmaengine drivers as the architecture precludes separating the ->prep from ->submit. In these cases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify the async_tx allocator to only return channels that support all of the required asynchronous operations. For example MD_RAID456=y selects support for asynchronous xor, xor validate, pq, pq validate, and memcpy. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=y any channel with all these capabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to quickly locate compatible channels with the guarantee that dependency chains will remain on one channel. When ASYNC_TX_DISABLE_CHANNEL_SWITCH=n async_tx_find_channel() may select channels that lead to operation chains that need to cross channel boundaries using the async_tx channel switch capability. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
124 lines
3.2 KiB
Plaintext
124 lines
3.2 KiB
Plaintext
#
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# DMA engine configuration
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#
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menuconfig DMADEVICES
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bool "DMA Engine support"
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depends on HAS_DMA
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help
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DMA engines can do asynchronous data transfers without
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involving the host CPU. Currently, this framework can be
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used to offload memory copies in the network stack and
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RAID operations in the MD driver. This menu only presents
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DMA Device drivers supported by the configured arch, it may
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be empty in some cases.
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if DMADEVICES
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comment "DMA Devices"
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config ASYNC_TX_DISABLE_CHANNEL_SWITCH
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bool
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config INTEL_IOATDMA
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tristate "Intel I/OAT DMA support"
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depends on PCI && X86
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select DMA_ENGINE
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select DCA
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select ASYNC_TX_DISABLE_CHANNEL_SWITCH
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help
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Enable support for the Intel(R) I/OAT DMA engine present
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in recent Intel Xeon chipsets.
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Say Y here if you have such a chipset.
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If unsure, say N.
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config INTEL_IOP_ADMA
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tristate "Intel IOP ADMA support"
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depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
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select DMA_ENGINE
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help
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Enable support for the Intel(R) IOP Series RAID engines.
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config DW_DMAC
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tristate "Synopsys DesignWare AHB DMA support"
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depends on AVR32
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select DMA_ENGINE
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default y if CPU_AT32AP7000
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help
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Support the Synopsys DesignWare AHB DMA controller. This
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can be integrated in chips such as the Atmel AT32ap7000.
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config FSL_DMA
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tristate "Freescale Elo and Elo Plus DMA support"
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depends on FSL_SOC
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select DMA_ENGINE
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---help---
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Enable support for the Freescale Elo and Elo Plus DMA controllers.
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The Elo is the DMA controller on some 82xx and 83xx parts, and the
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Elo Plus is the DMA controller on 85xx and 86xx parts.
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config MV_XOR
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bool "Marvell XOR engine support"
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depends on PLAT_ORION
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select DMA_ENGINE
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---help---
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Enable support for the Marvell XOR engine.
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config MX3_IPU
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bool "MX3x Image Processing Unit support"
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depends on ARCH_MX3
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select DMA_ENGINE
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default y
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help
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If you plan to use the Image Processing unit in the i.MX3x, say
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Y here. If unsure, select Y.
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config MX3_IPU_IRQS
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int "Number of dynamically mapped interrupts for IPU"
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depends on MX3_IPU
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range 2 137
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default 4
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help
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Out of 137 interrupt sources on i.MX31 IPU only very few are used.
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To avoid bloating the irq_desc[] array we allocate a sufficient
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number of IRQ slots and map them dynamically to specific sources.
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config DMA_ENGINE
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bool
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comment "DMA Clients"
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depends on DMA_ENGINE
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config NET_DMA
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bool "Network: TCP receive copy offload"
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depends on DMA_ENGINE && NET
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default (INTEL_IOATDMA || FSL_DMA)
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help
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This enables the use of DMA engines in the network stack to
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offload receive copy-to-user operations, freeing CPU cycles.
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Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
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say N.
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config ASYNC_TX_DMA
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bool "Async_tx: Offload support for the async_tx api"
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depends on DMA_ENGINE
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help
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This allows the async_tx api to take advantage of offload engines for
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memcpy, memset, xor, and raid6 p+q operations. If your platform has
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a dma engine that can perform raid operations and you have enabled
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MD_RAID456 say Y.
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If unsure, say N.
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config DMATEST
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tristate "DMA Test client"
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depends on DMA_ENGINE
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help
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Simple DMA test client. Say N unless you're debugging a
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DMA Device driver.
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endif
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