mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 19:53:59 +08:00
830145796a
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has made for plaforms based on EXYNOS4 SoCs. But since upcoming Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most codes in current mach-exynos4, one mach-exynos directory will be used for them. This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos) but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to avoid changing in driver side. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
134 lines
2.6 KiB
C
134 lines
2.6 KiB
C
/* linux arch/arm/mach-exynos4/hotplug.c
|
|
*
|
|
* Cloned from linux/arch/arm/mach-realview/hotplug.c
|
|
*
|
|
* Copyright (C) 2002 ARM Ltd.
|
|
* All Rights Reserved
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/smp.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <asm/cacheflush.h>
|
|
|
|
#include <mach/regs-pmu.h>
|
|
|
|
extern volatile int pen_release;
|
|
|
|
static inline void cpu_enter_lowpower(void)
|
|
{
|
|
unsigned int v;
|
|
|
|
flush_cache_all();
|
|
asm volatile(
|
|
" mcr p15, 0, %1, c7, c5, 0\n"
|
|
" mcr p15, 0, %1, c7, c10, 4\n"
|
|
/*
|
|
* Turn off coherency
|
|
*/
|
|
" mrc p15, 0, %0, c1, c0, 1\n"
|
|
" bic %0, %0, %3\n"
|
|
" mcr p15, 0, %0, c1, c0, 1\n"
|
|
" mrc p15, 0, %0, c1, c0, 0\n"
|
|
" bic %0, %0, %2\n"
|
|
" mcr p15, 0, %0, c1, c0, 0\n"
|
|
: "=&r" (v)
|
|
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
|
|
: "cc");
|
|
}
|
|
|
|
static inline void cpu_leave_lowpower(void)
|
|
{
|
|
unsigned int v;
|
|
|
|
asm volatile(
|
|
"mrc p15, 0, %0, c1, c0, 0\n"
|
|
" orr %0, %0, %1\n"
|
|
" mcr p15, 0, %0, c1, c0, 0\n"
|
|
" mrc p15, 0, %0, c1, c0, 1\n"
|
|
" orr %0, %0, %2\n"
|
|
" mcr p15, 0, %0, c1, c0, 1\n"
|
|
: "=&r" (v)
|
|
: "Ir" (CR_C), "Ir" (0x40)
|
|
: "cc");
|
|
}
|
|
|
|
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
|
|
{
|
|
for (;;) {
|
|
|
|
/* make cpu1 to be turned off at next WFI command */
|
|
if (cpu == 1)
|
|
__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
|
|
|
|
/*
|
|
* here's the WFI
|
|
*/
|
|
asm(".word 0xe320f003\n"
|
|
:
|
|
:
|
|
: "memory", "cc");
|
|
|
|
if (pen_release == cpu_logical_map(cpu)) {
|
|
/*
|
|
* OK, proper wakeup, we're done
|
|
*/
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Getting here, means that we have come out of WFI without
|
|
* having been woken up - this shouldn't happen
|
|
*
|
|
* Just note it happening - when we're woken, we can report
|
|
* its occurrence.
|
|
*/
|
|
(*spurious)++;
|
|
}
|
|
}
|
|
|
|
int platform_cpu_kill(unsigned int cpu)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* platform-specific code to shutdown a CPU
|
|
*
|
|
* Called with IRQs disabled
|
|
*/
|
|
void platform_cpu_die(unsigned int cpu)
|
|
{
|
|
int spurious = 0;
|
|
|
|
/*
|
|
* we're ready for shutdown now, so do it
|
|
*/
|
|
cpu_enter_lowpower();
|
|
platform_do_lowpower(cpu, &spurious);
|
|
|
|
/*
|
|
* bring this CPU back into the world of cache
|
|
* coherency, and then restore interrupts
|
|
*/
|
|
cpu_leave_lowpower();
|
|
|
|
if (spurious)
|
|
pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
|
|
}
|
|
|
|
int platform_cpu_disable(unsigned int cpu)
|
|
{
|
|
/*
|
|
* we don't allow CPU 0 to be shutdown (it is still too special
|
|
* e.g. clock tick interrupts)
|
|
*/
|
|
return cpu == 0 ? -EPERM : 0;
|
|
}
|