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304bceda6a
Fundamental model of the current Linux kernel is to lazily init and restore FPU instead of restoring the task state during context switch. This changes that fundamental lazy model to the non-lazy model for the processors supporting xsave feature. Reasons driving this model change are: i. Newer processors support optimized state save/restore using xsaveopt and xrstor by tracking the INIT state and MODIFIED state during context-switch. This is faster than modifying the cr0.TS bit which has serializing semantics. ii. Newer glibc versions use SSE for some of the optimized copy/clear routines. With certain workloads (like boot, kernel-compilation etc), application completes its work with in the first 5 task switches, thus taking upto 5 #DNA traps with the kernel not getting a chance to apply the above mentioned pre-load heuristic. iii. Some xstate features (like AMD's LWP feature) don't honor the cr0.TS bit and thus will not work correctly in the presence of lazy restore. Non-lazy state restore is needed for enabling such features. Some data on a two socket SNB system: * Saved 20K DNA exceptions during boot on a two socket SNB system. * Saved 50K DNA exceptions during kernel-compilation workload. * Improved throughput of the AVX based checksumming function inside the kernel by ~15% as xsave/xrstor is faster than the serializing clts/stts pair. Also now kernel_fpu_begin/end() relies on the patched alternative instructions. So move check_fpu() which uses the kernel_fpu_begin/end() after alternative_instructions(). Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Link: http://lkml.kernel.org/r/1345842782-24175-7-git-send-email-suresh.b.siddha@intel.com Merge 32-bit boot fix from, Link: http://lkml.kernel.org/r/1347300665-6209-4-git-send-email-suresh.b.siddha@intel.com Cc: Jim Kukunas <james.t.kukunas@linux.intel.com> Cc: NeilBrown <neilb@suse.de> Cc: Avi Kivity <avi@redhat.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
180 lines
3.8 KiB
C
180 lines
3.8 KiB
C
/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Cyrix stuff, June 1998 by:
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* - Rafael R. Reilova (moved everything from head.S),
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* <rreilova@ececs.uc.edu>
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* - Channing Corn (tests & fixes),
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* - Andrew D. Balsa (code cleanup).
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*/
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#include <linux/init.h>
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#include <linux/utsname.h>
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#include <asm/bugs.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/i387.h>
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#include <asm/msr.h>
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#include <asm/paravirt.h>
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#include <asm/alternative.h>
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static int __init no_halt(char *s)
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{
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WARN_ONCE(1, "\"no-hlt\" is deprecated, please use \"idle=poll\"\n");
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boot_cpu_data.hlt_works_ok = 0;
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return 1;
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}
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__setup("no-hlt", no_halt);
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static int __init no_387(char *s)
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{
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boot_cpu_data.hard_math = 0;
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write_cr0(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP | read_cr0());
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return 1;
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}
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__setup("no387", no_387);
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static double __initdata x = 4195835.0;
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static double __initdata y = 3145727.0;
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/*
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* This used to check for exceptions..
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* However, it turns out that to support that,
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* the XMM trap handlers basically had to
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* be buggy. So let's have a correct XMM trap
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* handler, and forget about printing out
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* some status at boot.
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*
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* We should really only care about bugs here
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* anyway. Not features.
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*/
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static void __init check_fpu(void)
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{
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s32 fdiv_bug;
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if (!boot_cpu_data.hard_math) {
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#ifndef CONFIG_MATH_EMULATION
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pr_emerg("No coprocessor found and no math emulation present\n");
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pr_emerg("Giving up\n");
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for (;;) ;
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#endif
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return;
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}
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kernel_fpu_begin();
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/*
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* trap_init() enabled FXSR and company _before_ testing for FP
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* problems here.
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*
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* Test for the divl bug..
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*/
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__asm__("fninit\n\t"
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"fldl %1\n\t"
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"fdivl %2\n\t"
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"fmull %2\n\t"
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"fldl %1\n\t"
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"fsubp %%st,%%st(1)\n\t"
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"fistpl %0\n\t"
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"fwait\n\t"
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"fninit"
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: "=m" (*&fdiv_bug)
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: "m" (*&x), "m" (*&y));
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kernel_fpu_end();
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boot_cpu_data.fdiv_bug = fdiv_bug;
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if (boot_cpu_data.fdiv_bug)
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pr_warn("Hmm, FPU with FDIV bug\n");
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}
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static void __init check_hlt(void)
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{
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if (boot_cpu_data.x86 >= 5 || paravirt_enabled())
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return;
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pr_info("Checking 'hlt' instruction... ");
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if (!boot_cpu_data.hlt_works_ok) {
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pr_cont("disabled\n");
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return;
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}
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halt();
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halt();
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halt();
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halt();
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pr_cont("OK\n");
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}
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/*
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* Most 386 processors have a bug where a POPAD can lock the
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* machine even from user space.
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*/
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static void __init check_popad(void)
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{
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#ifndef CONFIG_X86_POPAD_OK
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int res, inp = (int) &res;
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pr_info("Checking for popad bug... ");
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__asm__ __volatile__(
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"movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx "
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: "=&a" (res)
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: "d" (inp)
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: "ecx", "edi");
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/*
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* If this fails, it means that any user program may lock the
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* CPU hard. Too bad.
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*/
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if (res != 12345678)
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pr_cont("Buggy\n");
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else
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pr_cont("OK\n");
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#endif
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}
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/*
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* Check whether we are able to run this kernel safely on SMP.
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*
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* - In order to run on a i386, we need to be compiled for i386
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* (for due to lack of "invlpg" and working WP on a i386)
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* - In order to run on anything without a TSC, we need to be
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* compiled for a i486.
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*/
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static void __init check_config(void)
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{
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/*
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* We'd better not be a i386 if we're configured to use some
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* i486+ only features! (WP works in supervisor mode and the
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* new "invlpg" and "bswap" instructions)
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*/
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#if defined(CONFIG_X86_WP_WORKS_OK) || defined(CONFIG_X86_INVLPG) || \
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defined(CONFIG_X86_BSWAP)
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if (boot_cpu_data.x86 == 3)
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panic("Kernel requires i486+ for 'invlpg' and other features");
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#endif
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}
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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#ifndef CONFIG_SMP
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pr_info("CPU: ");
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print_cpu_info(&boot_cpu_data);
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#endif
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check_config();
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check_hlt();
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check_popad();
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init_utsname()->machine[1] =
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'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
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alternative_instructions();
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/*
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* kernel_fpu_begin/end() in check_fpu() relies on the patched
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* alternative instructions.
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*/
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check_fpu();
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}
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