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https://github.com/edk2-porting/linux-next.git
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b274776c54
A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUSUyKmCrR//JCVInAQIN8RAAnb/uPytmlMjn5yCksF4Mvb/FVbn/TVwz KRIGpCHOzyKK1q7pM8NRUVWfjW2SZqbXJFqx6zBGKSlDPvFTOhsLyyupU+Tnyu5W IX4eIUBwb+a6H7XDHw0X2YI8uHzi5RNLhne0A1QyDKcnuHs1LDAttXnJHaK4Ap6Y NN2YFt3l3ld7DXWXJtMsw5v8lC10aeIFGTvXefaPDAdeMLivmI57qEUMDXknNr7W Odz/Rc0/cw3BNBVl/zNHA0jw7FOjKAymCYYNUa4xDCJEr+JnIRTqizd0N/YIIC7x aA2xjJ3oKUFyF51yiJE6nFuTyJznhwtehc+uiMOSIkjrPLym52LEHmd7G5Yqlmjz oiei09qBb870q3lGxwfht9iaeIwYgQFYGfD0yW5QWArCO5pxhtCPLPH7YZNZtcQd ZJRSGGqT/ljBz3bm0K9OLESeeTTN7+Nxvtpiz/CD+Piegz0gWJzDYJRTzkJ3UWpA WTVhVQdWUeX2JrNkgM7Z3Tu8iXOe+LIEs7kVXGJZSREmIIZiRvR36UrODZtAkp9I 7YQ+srX/uaR832pgK0RrHK0zY0psU6MmIvhYxJZFbx7keiPA9eH6drb0x7tGqcUD FzEUzvcZvyqppndfBi+R60H/YKAhJDEXdwxzo6dyCpPQaW1T9GnzIqXuE1zin+Aw X7Y8YywMbHI= =DvgJ -----END PGP SIGNATURE----- Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Arnd Bergmann: "A large number of cleanups, all over the platforms. This is dominated largely by the Samsung platforms (s3c, s5p, exynos) and a few of the others moving code out of arch/arm into more appropriate subsystems. The clocksource and irqchip drivers are now abstracted to the point where platforms that are already cleaned up do not need to even specify the driver they use, it can all get configured from the device tree as we do for normal device drivers. The clocksource changes basically touch every single platform in the process. We further clean up the use of platform specific header files here, with the goal of turning more of the platforms over to being "multiplatform" enabled, which implies that they cannot expose their headers to architecture independent code any more. It is expected that no functional changes are part of the cleanup. The overall reduction in total code lines is mostly the result of removing broken and obsolete code." * tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits) ARM: mvebu: correct gated clock documentation ARM: kirkwood: add missing include for nsa310 ARM: exynos: move exynos4210-combiner to drivers/irqchip mfd: db8500-prcmu: update resource passing drivers/db8500-cpufreq: delete dangling include ARM: at91: remove NEOCORE 926 board sunxi: Cleanup the reset code and add meaningful registers defines ARM: S3C24XX: header mach/regs-mem.h local ARM: S3C24XX: header mach/regs-power.h local ARM: S3C24XX: header mach/regs-s3c2412-mem.h local ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/ ARM: S3C24XX: transform s3c2443 subirqs into new structure ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs ARM: S3C24XX: move s3c2443 irq code to irq.c ARM: S3C24XX: transform s3c2416 irqs into new structure ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs ARM: S3C24XX: move s3c2416 irq init to common irq code ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property ARM: S3C24XX: Move irq syscore-ops to irq-pm clocksource: always define CLOCKSOURCE_OF_DECLARE ...
451 lines
11 KiB
C
451 lines
11 KiB
C
/*
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* OMAP WakeupGen Source file
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*
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* OMAP WakeupGen is the interrupt controller extension used along
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* with ARM GIC to wake the CPU out from low power states on
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* external interrupts. It is responsible for generating wakeup
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* event from the incoming interrupts and enable bits. It is
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* implemented in MPU always ON power domain. During normal operation,
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* WakeupGen delivers external interrupts directly to the GIC.
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/notifier.h>
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#include <linux/cpu_pm.h>
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#include <linux/irqchip/arm-gic.h>
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#include "omap-wakeupgen.h"
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#include "omap-secure.h"
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#include "soc.h"
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#include "omap4-sar-layout.h"
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#include "common.h"
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#define MAX_NR_REG_BANKS 5
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#define MAX_IRQS 160
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#define WKG_MASK_ALL 0x00000000
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#define WKG_UNMASK_ALL 0xffffffff
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#define CPU_ENA_OFFSET 0x400
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#define CPU0_ID 0x0
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#define CPU1_ID 0x1
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#define OMAP4_NR_BANKS 4
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#define OMAP4_NR_IRQS 128
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static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[MAX_IRQS];
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static unsigned int irq_banks = MAX_NR_REG_BANKS;
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static unsigned int max_irqs = MAX_IRQS;
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static unsigned int omap_secure_apis;
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/*
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* Static helper functions.
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*/
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static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
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{
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return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
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{
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__raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
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(cpu * CPU_ENA_OFFSET) + (idx * 4));
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}
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static inline void sar_writel(u32 val, u32 offset, u8 idx)
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{
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__raw_writel(val, sar_base + offset + (idx * 4));
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}
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static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
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{
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unsigned int spi_irq;
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/*
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* PPIs and SGIs are not supported.
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*/
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if (irq < OMAP44XX_IRQ_GIC_START)
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return -EINVAL;
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/*
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* Subtract the GIC offset.
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*/
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spi_irq = irq - OMAP44XX_IRQ_GIC_START;
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if (spi_irq > MAX_IRQS) {
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pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
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return -EINVAL;
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}
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/*
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* Each WakeupGen register controls 32 interrupt.
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* i.e. 1 bit per SPI IRQ
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*/
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*reg_index = spi_irq >> 5;
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*bit_posn = spi_irq %= 32;
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return 0;
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}
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static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val &= ~BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
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{
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u32 val, bit_number;
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u8 i;
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if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
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return;
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val = wakeupgen_readl(i, cpu);
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val |= BIT(bit_number);
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wakeupgen_writel(val, i, cpu);
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}
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/*
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* Architecture specific Mask extension
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*/
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static void wakeupgen_mask(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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/*
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* Architecture specific Unmask extension
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*/
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static void wakeupgen_unmask(struct irq_data *d)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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_wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
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static void _wakeupgen_save_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
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}
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static void _wakeupgen_restore_masks(unsigned int cpu)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
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}
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static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
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{
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u8 i;
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for (i = 0; i < irq_banks; i++)
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wakeupgen_writel(reg, i, cpu);
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}
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/*
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* Mask or unmask all interrupts on given CPU.
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* 0 = Mask all interrupts on the 'cpu'
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* 1 = Unmask all interrupts on the 'cpu'
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* Ensure that the initial mask is maintained. This is faster than
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* iterating through GIC registers to arrive at the correct masks.
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*/
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static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&wakeupgen_lock, flags);
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if (set) {
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_wakeupgen_save_masks(cpu);
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_wakeupgen_set_all(cpu, WKG_MASK_ALL);
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} else {
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_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
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_wakeupgen_restore_masks(cpu);
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}
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raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
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}
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#endif
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#ifdef CONFIG_CPU_PM
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static inline void omap4_irq_save_context(void)
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{
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u32 i, val;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 127 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
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/*
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* Disable the secure interrupts for CPUx. The restore
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* code blindly restores secure and non-secure interrupt
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* masks from SAR RAM. Secure interrupts are not suppose
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* to be enabled from HLOS. So overwrite the SAR location
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* so that the secure interrupt remains disabled.
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*/
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
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__raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
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/* Save SyncReq generation logic */
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val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
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__raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
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__raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
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/* Set the Backup Bit Mask status */
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val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
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}
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static inline void omap5_irq_save_context(void)
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{
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u32 i, val;
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for (i = 0; i < irq_banks; i++) {
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/* Save the CPUx interrupt mask for IRQ 0 to 159 */
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val = wakeupgen_readl(i, 0);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
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val = wakeupgen_readl(i, 1);
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sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
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sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
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}
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/* Save AuxBoot* registers */
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
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val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
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__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
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/* Set the Backup Bit Mask status */
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val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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val |= SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
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}
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/*
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* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
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* ROM code. WakeupGen IP is integrated along with GIC to manage the
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* interrupt wakeups from CPU low power states. It manages
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* masking/unmasking of Shared peripheral interrupts(SPI). So the
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* interrupt enable/disable control should be in sync and consistent
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* at WakeupGen and GIC so that interrupts are not lost.
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*/
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static void irq_save_context(void)
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{
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if (!sar_base)
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sar_base = omap4_get_sar_ram_base();
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if (soc_is_omap54xx())
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omap5_irq_save_context();
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else
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omap4_irq_save_context();
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}
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/*
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* Clear WakeupGen SAR backup status.
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*/
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static void irq_sar_clear(void)
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{
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u32 val;
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u32 offset = SAR_BACKUP_STATUS_OFFSET;
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if (soc_is_omap54xx())
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offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
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val = __raw_readl(sar_base + offset);
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val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
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__raw_writel(val, sar_base + offset);
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}
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/*
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* Save GIC and Wakeupgen interrupt context using secure API
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* for HS/EMU devices.
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*/
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static void irq_save_secure_context(void)
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{
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u32 ret;
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ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
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FLAG_START_CRITICAL,
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0, 0, 0, 0, 0);
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if (ret != API_HAL_RET_VALUE_OK)
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pr_err("GIC and Wakeupgen context save failed\n");
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}
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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unsigned int cpu = (unsigned int)hcpu;
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switch (action) {
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case CPU_ONLINE:
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wakeupgen_irqmask_all(cpu, 0);
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break;
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case CPU_DEAD:
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wakeupgen_irqmask_all(cpu, 1);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block __refdata irq_hotplug_notifier = {
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.notifier_call = irq_cpu_hotplug_notify,
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};
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static void __init irq_hotplug_init(void)
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{
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register_hotcpu_notifier(&irq_hotplug_notifier);
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}
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#else
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static void __init irq_hotplug_init(void)
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{}
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#endif
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#ifdef CONFIG_CPU_PM
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static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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{
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switch (cmd) {
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case CPU_CLUSTER_PM_ENTER:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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irq_save_context();
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else
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irq_save_secure_context();
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break;
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case CPU_CLUSTER_PM_EXIT:
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if (omap_type() == OMAP2_DEVICE_TYPE_GP)
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irq_sar_clear();
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block irq_notifier_block = {
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.notifier_call = irq_notifier,
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};
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static void __init irq_pm_init(void)
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{
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/* FIXME: Remove this when MPU OSWR support is added */
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if (!soc_is_omap54xx())
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cpu_pm_register_notifier(&irq_notifier_block);
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}
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#else
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static void __init irq_pm_init(void)
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{}
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#endif
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void __iomem *omap_get_wakeupgen_base(void)
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{
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return wakeupgen_base;
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}
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int omap_secure_apis_support(void)
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{
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return omap_secure_apis;
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}
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/*
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* Initialise the wakeupgen module.
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*/
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int __init omap_wakeupgen_init(void)
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{
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int i;
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unsigned int boot_cpu = smp_processor_id();
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/* Not supported on OMAP4 ES1.0 silicon */
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
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return -EPERM;
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}
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/* Static mapping, never released */
|
|
wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
|
|
if (WARN_ON(!wakeupgen_base))
|
|
return -ENOMEM;
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
irq_banks = OMAP4_NR_BANKS;
|
|
max_irqs = OMAP4_NR_IRQS;
|
|
omap_secure_apis = 1;
|
|
}
|
|
|
|
/* Clear all IRQ bitmasks at wakeupGen level */
|
|
for (i = 0; i < irq_banks; i++) {
|
|
wakeupgen_writel(0, i, CPU0_ID);
|
|
wakeupgen_writel(0, i, CPU1_ID);
|
|
}
|
|
|
|
/*
|
|
* Override GIC architecture specific functions to add
|
|
* OMAP WakeupGen interrupt controller along with GIC
|
|
*/
|
|
gic_arch_extn.irq_mask = wakeupgen_mask;
|
|
gic_arch_extn.irq_unmask = wakeupgen_unmask;
|
|
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
|
|
|
|
/*
|
|
* FIXME: Add support to set_smp_affinity() once the core
|
|
* GIC code has necessary hooks in place.
|
|
*/
|
|
|
|
/* Associate all the IRQs to boot CPU like GIC init does. */
|
|
for (i = 0; i < max_irqs; i++)
|
|
irq_target_cpu[i] = boot_cpu;
|
|
|
|
irq_hotplug_init();
|
|
irq_pm_init();
|
|
|
|
return 0;
|
|
}
|