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c531fb27e9
On all shmobile ARM SoCs, loop-based delays may complete early, which
can be after only 1/3 (Cortex A9) or 1/2 (Cortex A7 or A15) of the
minimum required time.
This is caused by calculating preset_lpj based on incorrect assumptions
about the number of clock cycles per loop:
- All of Cortex A7, A9, and A15 run __loop_delay() at 1 loop per
CPU clock cycle,
- As of commit 11d4bb1bd0 ("ARM: 7907/1: lib: delay-loop: Add
align directive to fix BogoMIPS calculation"), Cortex A8 runs
__loop_delay() at 1 loop per 2 instead of 3 CPU clock cycles.
On SoCs with Cortex A7 and/or A15 CPU cores, this went unnoticed, as
delays use the ARM arch timer if available. R-Car Gen2 doesn't work if
the arch timer is disabled. However, APE6 can be used without the arch
timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
/*
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* SH-Mobile Timer
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2002 - 2009 Paul Mundt
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include "common.h"
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static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
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unsigned int mult, unsigned int div)
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{
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/* calculate a worst-case loops-per-jiffy value
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* based on maximum cpu core hz setting and the
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* __delay() implementation in arch/arm/lib/delay.S
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*
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* this will result in a longer delay than expected
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* when the cpu core runs on lower frequencies.
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*/
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unsigned int value = HZ * div / mult;
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if (!preset_lpj)
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preset_lpj = max_cpu_core_hz / value;
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}
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void __init shmobile_init_delay(void)
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{
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struct device_node *np, *cpus;
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unsigned int div = 0;
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bool has_arch_timer = false;
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u32 max_freq = 0;
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cpus = of_find_node_by_path("/cpus");
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if (!cpus)
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return;
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for_each_child_of_node(cpus, np) {
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u32 freq;
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if (!of_property_read_u32(np, "clock-frequency", &freq))
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max_freq = max(max_freq, freq);
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if (of_device_is_compatible(np, "arm,cortex-a8")) {
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div = 2;
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} else if (of_device_is_compatible(np, "arm,cortex-a9")) {
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div = 1;
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} else if (of_device_is_compatible(np, "arm,cortex-a7") ||
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of_device_is_compatible(np, "arm,cortex-a15")) {
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div = 1;
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has_arch_timer = true;
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}
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}
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of_node_put(cpus);
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if (!max_freq || !div)
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return;
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if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
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shmobile_setup_delay_hz(max_freq, 1, div);
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}
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