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The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> |
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.. | ||
clkdev.h | ||
clock.h | ||
dma-mapping.h | ||
hardirq.h | ||
irq.h | ||
irqflags.h | ||
Kbuild | ||
megamod-pic.h | ||
processor.h | ||
sigcontext.h | ||
signal.h | ||
syscalls.h | ||
thread_info.h | ||
timer64.h | ||
timex.h | ||
traps.h | ||
unistd.h |