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2f47f44790
This provides a method for supporting fixed PMB mappings inherited from the bootloader, as an alternative to the dynamic PMB mapping currently used by the kernel. In the future these methods will be combined. P1/P2 area is handled like a regular 29-bit physical address, and local bus device are assigned P3 area addresses. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Kaz Kojima
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*
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* Defitions for the address spaces of the SH CPUs.
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*/
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#ifndef __ASM_SH_ADDRSPACE_H
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#define __ASM_SH_ADDRSPACE_H
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#ifdef __KERNEL__
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#include <cpu/addrspace.h>
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/* If this CPU supports segmentation, hook up the helpers */
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#ifdef P1SEG
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/*
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[ P0/U0 (virtual) ] 0x00000000 <------ User space
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[ P1 (fixed) cached ] 0x80000000 <------ Kernel space
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[ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access
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[ P3 (virtual) cached] 0xC0000000 <------ vmalloced area
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[ P4 control ] 0xE0000000
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*/
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/* Returns the privileged segment base of a given address */
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#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
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/* Returns the physical address of a PnSEG (n=1,2) address */
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#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
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#if defined(CONFIG_29BIT) || defined(CONFIG_PMB_FIXED)
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/*
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* Map an address to a certain privileged segment
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*/
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#define P1SEGADDR(a) \
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((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
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#define P2SEGADDR(a) \
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((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
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#define P3SEGADDR(a) \
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((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
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#define P4SEGADDR(a) \
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((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
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#endif /* 29BIT || PMB_FIXED */
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#endif /* P1SEG */
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/* Check if an address can be reached in 29 bits */
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#define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000)
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#ifdef CONFIG_SH_STORE_QUEUES
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/*
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* This is a special case for the SH-4 store queues, as pages for this
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* space still need to be faulted in before it's possible to flush the
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* store queue cache for writeout to the remapped region.
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*/
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#define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000)
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#else
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#define P3_ADDR_MAX P4SEG
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_ADDRSPACE_H */
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