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aec2927b59
This patch adds the capability to support RZ/A1 SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas USB driver RZ/A initialization and power control
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*
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* Copyright (C) 2018 Chris Brandt
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* Copyright (C) 2018 Renesas Electronics Corporation
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include "common.h"
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#include "rza.h"
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static int usbhs_rza1_hardware_init(struct platform_device *pdev)
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{
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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struct device_node *usb_x1_clk, *extal_clk;
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u32 freq_usb = 0, freq_extal = 0;
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/* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
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usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
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extal_clk = of_find_node_by_name(NULL, "extal");
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of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
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of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
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if (freq_usb == 0) {
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if (freq_extal == 12000000) {
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/* Select 12MHz XTAL */
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usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
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} else {
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dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
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return -EIO;
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}
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}
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/* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
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usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
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udelay(1000);
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usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
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return 0;
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}
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static int usbhs_rza_get_id(struct platform_device *pdev)
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{
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return USBHS_GADGET;
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}
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const struct renesas_usbhs_platform_callback usbhs_rza1_ops = {
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.hardware_init = usbhs_rza1_hardware_init,
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.get_id = usbhs_rza_get_id,
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};
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