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3f65ce4d14
The attached patches provides part 5 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
375 lines
5.8 KiB
ArmAsm
375 lines
5.8 KiB
ArmAsm
/*
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* arch/xtensa/mm/misc.S
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*
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* Miscellaneous assembly functions.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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*/
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/* Note: we might want to implement some of the loops as zero-overhead-loops,
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* where applicable and if supported by the processor.
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*/
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#include <linux/linkage.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <xtensa/cacheasm.h>
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#include <xtensa/cacheattrasm.h>
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/* clear_page (page) */
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ENTRY(clear_page)
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entry a1, 16
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addi a4, a2, PAGE_SIZE
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movi a3, 0
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1: s32i a3, a2, 0
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s32i a3, a2, 4
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s32i a3, a2, 8
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s32i a3, a2, 12
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s32i a3, a2, 16
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s32i a3, a2, 20
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s32i a3, a2, 24
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s32i a3, a2, 28
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addi a2, a2, 32
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blt a2, a4, 1b
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retw
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/*
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* copy_page (void *to, void *from)
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* a2 a3
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*/
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ENTRY(copy_page)
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entry a1, 16
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addi a4, a2, PAGE_SIZE
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1: l32i a5, a3, 0
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l32i a6, a3, 4
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l32i a7, a3, 8
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s32i a5, a2, 0
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s32i a6, a2, 4
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s32i a7, a2, 8
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l32i a5, a3, 12
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l32i a6, a3, 16
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l32i a7, a3, 20
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s32i a5, a2, 12
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s32i a6, a2, 16
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s32i a7, a2, 20
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l32i a5, a3, 24
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l32i a6, a3, 28
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s32i a5, a2, 24
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s32i a6, a2, 28
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addi a2, a2, 32
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addi a3, a3, 32
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blt a2, a4, 1b
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retw
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/*
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* void __flush_invalidate_cache_all(void)
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*/
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ENTRY(__flush_invalidate_cache_all)
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entry sp, 16
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dcache_writeback_inv_all a2, a3
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icache_invalidate_all a2, a3
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retw
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/*
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* void __invalidate_icache_all(void)
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*/
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ENTRY(__invalidate_icache_all)
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entry sp, 16
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icache_invalidate_all a2, a3
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retw
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/*
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* void __flush_invalidate_dcache_all(void)
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*/
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ENTRY(__flush_invalidate_dcache_all)
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entry sp, 16
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dcache_writeback_inv_all a2, a3
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retw
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/*
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* void __flush_invalidate_cache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_invalidate_cache_range)
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entry sp, 16
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mov a4, a2
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mov a5, a3
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dcache_writeback_inv_region a4, a5, a6
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icache_invalidate_region a2, a3, a4
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retw
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/*
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* void __invalidate_icache_page(ulong start)
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*/
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ENTRY(__invalidate_icache_page)
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entry sp, 16
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movi a3, PAGE_SIZE
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icache_invalidate_region a2, a3, a4
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retw
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/*
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* void __invalidate_dcache_page(ulong start)
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*/
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ENTRY(__invalidate_dcache_page)
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entry sp, 16
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movi a3, PAGE_SIZE
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dcache_invalidate_region a2, a3, a4
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retw
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/*
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* void __invalidate_icache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_icache_range)
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entry sp, 16
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icache_invalidate_region a2, a3, a4
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retw
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/*
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* void __invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__invalidate_dcache_range)
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entry sp, 16
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dcache_invalidate_region a2, a3, a4
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retw
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/*
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* void __flush_dcache_page(ulong start)
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*/
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ENTRY(__flush_dcache_page)
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entry sp, 16
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movi a3, PAGE_SIZE
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dcache_writeback_region a2, a3, a4
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retw
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/*
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* void __flush_invalidate_dcache_page(ulong start)
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*/
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ENTRY(__flush_invalidate_dcache_page)
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entry sp, 16
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movi a3, PAGE_SIZE
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dcache_writeback_inv_region a2, a3, a4
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retw
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/*
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* void __flush_invalidate_dcache_range(ulong start, ulong size)
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*/
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ENTRY(__flush_invalidate_dcache_range)
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entry sp, 16
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dcache_writeback_inv_region a2, a3, a4
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retw
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/*
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* void __invalidate_dcache_all(void)
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*/
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ENTRY(__invalidate_dcache_all)
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entry sp, 16
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dcache_invalidate_all a2, a3
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retw
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/*
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* void __flush_invalidate_dcache_page_phys(ulong start)
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*/
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ENTRY(__flush_invalidate_dcache_page_phys)
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entry sp, 16
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movi a3, XCHAL_DCACHE_SIZE
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movi a4, PAGE_MASK | 1
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addi a2, a2, 1
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1: addi a3, a3, -XCHAL_DCACHE_LINESIZE
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ldct a6, a3
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dsync
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and a6, a6, a4
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beq a6, a2, 2f
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bgeui a3, 2, 1b
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retw
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2: diwbi a3, 0
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bgeui a3, 2, 1b
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retw
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ENTRY(check_dcache_low0)
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entry sp, 16
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movi a3, XCHAL_DCACHE_SIZE / 4
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movi a4, PAGE_MASK | 1
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addi a2, a2, 1
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1: addi a3, a3, -XCHAL_DCACHE_LINESIZE
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ldct a6, a3
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dsync
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and a6, a6, a4
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beq a6, a2, 2f
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bgeui a3, 2, 1b
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retw
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2: j 2b
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ENTRY(check_dcache_high0)
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entry sp, 16
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movi a5, XCHAL_DCACHE_SIZE / 4
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movi a3, XCHAL_DCACHE_SIZE / 2
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movi a4, PAGE_MASK | 1
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addi a2, a2, 1
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1: addi a3, a3, -XCHAL_DCACHE_LINESIZE
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addi a5, a5, -XCHAL_DCACHE_LINESIZE
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ldct a6, a3
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dsync
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and a6, a6, a4
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beq a6, a2, 2f
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bgeui a5, 2, 1b
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retw
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2: j 2b
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ENTRY(check_dcache_low1)
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entry sp, 16
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movi a5, XCHAL_DCACHE_SIZE / 4
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movi a3, XCHAL_DCACHE_SIZE * 3 / 4
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movi a4, PAGE_MASK | 1
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addi a2, a2, 1
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1: addi a3, a3, -XCHAL_DCACHE_LINESIZE
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addi a5, a5, -XCHAL_DCACHE_LINESIZE
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ldct a6, a3
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dsync
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and a6, a6, a4
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beq a6, a2, 2f
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bgeui a5, 2, 1b
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retw
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2: j 2b
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ENTRY(check_dcache_high1)
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entry sp, 16
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movi a5, XCHAL_DCACHE_SIZE / 4
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movi a3, XCHAL_DCACHE_SIZE
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movi a4, PAGE_MASK | 1
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addi a2, a2, 1
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1: addi a3, a3, -XCHAL_DCACHE_LINESIZE
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addi a5, a5, -XCHAL_DCACHE_LINESIZE
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ldct a6, a3
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dsync
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and a6, a6, a4
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beq a6, a2, 2f
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bgeui a5, 2, 1b
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retw
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2: j 2b
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/*
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* void __invalidate_icache_page_phys(ulong start)
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*/
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ENTRY(__invalidate_icache_page_phys)
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entry sp, 16
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movi a3, XCHAL_ICACHE_SIZE
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movi a4, PAGE_MASK | 1
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addi a2, a2, 1
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1: addi a3, a3, -XCHAL_ICACHE_LINESIZE
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lict a6, a3
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isync
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and a6, a6, a4
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beq a6, a2, 2f
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bgeui a3, 2, 1b
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retw
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2: iii a3, 0
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bgeui a3, 2, 1b
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retw
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#if 0
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movi a3, XCHAL_DCACHE_WAYS - 1
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movi a4, PAGE_SIZE
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1: mov a5, a2
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add a6, a2, a4
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2: diwbi a5, 0
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diwbi a5, XCHAL_DCACHE_LINESIZE
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diwbi a5, XCHAL_DCACHE_LINESIZE * 2
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diwbi a5, XCHAL_DCACHE_LINESIZE * 3
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addi a5, a5, XCHAL_DCACHE_LINESIZE * 4
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blt a5, a6, 2b
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addi a3, a3, -1
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addi a2, a2, XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS
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bgez a3, 1b
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retw
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ENTRY(__invalidate_icache_page_index)
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entry sp, 16
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movi a3, XCHAL_ICACHE_WAYS - 1
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movi a4, PAGE_SIZE
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1: mov a5, a2
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add a6, a2, a4
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2: iii a5, 0
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iii a5, XCHAL_ICACHE_LINESIZE
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iii a5, XCHAL_ICACHE_LINESIZE * 2
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iii a5, XCHAL_ICACHE_LINESIZE * 3
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addi a5, a5, XCHAL_ICACHE_LINESIZE * 4
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blt a5, a6, 2b
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addi a3, a3, -1
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addi a2, a2, XCHAL_ICACHE_SIZE / XCHAL_ICACHE_WAYS
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bgez a3, 2b
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retw
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#endif
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