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80515a5a2e
SPEAr3xx architecture includes shared/multiplexed irqs for certain set of devices. The multiplexor provides a single interrupt to parent interrupt controller (VIC) on behalf of a group of devices. There can be multiple groups available on SPEAr3xx variants but not exceeding 4. The number of devices in a group can differ, further they may share same set of status/mask registers spanning across different bit masks. Also in some cases the group may not have enable or other registers. This makes software little complex. Present implementation was non-DT and had few complex data structures to decipher banks, number of irqs supported, mask and registers involved. This patch simplifies the overall design and convert it in to DT. It also removes all registration from individual SoC files and bring them in to common shirq.c. Also updated the corresponding documentation for DT binding of shirq. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
264 lines
5.8 KiB
C
264 lines
5.8 KiB
C
/*
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* arch/arm/mach-spear3xx/spear310.c
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*
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* SPEAr310 machine source file
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*
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* Copyright (C) 2009-2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "SPEAr310: " fmt
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#include <linux/amba/pl08x.h>
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#include <linux/amba/serial.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/vic.h>
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#include <asm/mach/arch.h>
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#include <mach/generic.h>
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#include <mach/spear.h>
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#define SPEAR310_UART1_BASE UL(0xB2000000)
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#define SPEAR310_UART2_BASE UL(0xB2080000)
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#define SPEAR310_UART3_BASE UL(0xB2100000)
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#define SPEAR310_UART4_BASE UL(0xB2180000)
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#define SPEAR310_UART5_BASE UL(0xB2200000)
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/* DMAC platform data's slave info */
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struct pl08x_channel_data spear310_dma_info[] = {
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{
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.bus_id = "uart0_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart0_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "irda",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "adc",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "to_jpeg",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "from_jpeg",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart1_rx",
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.min_signal = 0,
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.max_signal = 0,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart1_tx",
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.min_signal = 1,
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.max_signal = 1,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart2_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart2_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart3_rx",
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.min_signal = 4,
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.max_signal = 4,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart3_tx",
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.min_signal = 5,
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.max_signal = 5,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart4_rx",
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.min_signal = 6,
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.max_signal = 6,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart4_tx",
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.min_signal = 7,
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.max_signal = 7,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart5_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart5_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras5_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras5_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras6_rx",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras6_tx",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras7_rx",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ras7_tx",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 1,
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.periph_buses = PL08X_AHB1,
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},
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};
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/* uart devices plat data */
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static struct amba_pl011_data spear310_uart_data[] = {
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{
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart1_tx",
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.dma_rx_param = "uart1_rx",
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}, {
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart2_tx",
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.dma_rx_param = "uart2_rx",
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}, {
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart3_tx",
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.dma_rx_param = "uart3_rx",
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}, {
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart4_tx",
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.dma_rx_param = "uart4_rx",
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}, {
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart5_tx",
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.dma_rx_param = "uart5_rx",
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},
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};
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/* Add SPEAr310 auxdata to pass platform data */
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static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
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&pl022_plat_data),
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OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
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&pl080_plat_data),
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OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
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&spear310_uart_data[0]),
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OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
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&spear310_uart_data[1]),
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OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
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&spear310_uart_data[2]),
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OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
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&spear310_uart_data[3]),
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OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
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&spear310_uart_data[4]),
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{}
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};
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static void __init spear310_dt_init(void)
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{
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pl080_plat_data.slave_channels = spear310_dma_info;
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pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
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of_platform_populate(NULL, of_default_bus_match_table,
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spear310_auxdata_lookup, NULL);
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}
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static const char * const spear310_dt_board_compat[] = {
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"st,spear310",
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"st,spear310-evb",
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NULL,
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};
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static void __init spear310_map_io(void)
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{
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spear3xx_map_io();
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}
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DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
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.map_io = spear310_map_io,
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.init_irq = spear3xx_dt_init_irq,
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.handle_irq = vic_handle_irq,
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.timer = &spear3xx_timer,
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.init_machine = spear310_dt_init,
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.restart = spear_restart,
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.dt_compat = spear310_dt_board_compat,
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MACHINE_END
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