Christoffer Dall 6d56111c92 KVM: arm/arm64: vgic: Fix GICC_PMR uaccess on GICv3 and clarify ABI ... As an oversight, for GICv2, we accidentally export the GICC_PMR register in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a word, meaning that userspace must always use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level. Since GICv3 supports the full 8 bits of priority masking in the ICH_VMCR, we have to fix the value we export when emulating a GICv2 on top of a hardware GICv3 and exporting the emulated GICv2 state to userspace. Take the chance to clarify this aspect of the ABI. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org>		2017-04-04 14:33:59 +02:00
..
arm-gic-common.h	irqchip/gic-v3: Parse and export virtual GIC information	2016-05-03 12:54:21 +02:00
arm-gic-v3.h	KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass	2017-03-06 10:30:57 +00:00
arm-gic.h	KVM: arm/arm64: vgic: Fix GICC_PMR uaccess on GICv3 and clarify ABI	2017-04-04 14:33:59 +02:00
arm-vic.h	irqchip: support cascaded VICs	2014-02-13 11:21:21 +01:00
chained_irq.h
ingenic.h	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	2015-06-21 21:53:10 +02:00
irq-omap-intc.h	irqchip: omap-intc: Remove unused legacy interface for omap2	2015-01-26 11:38:23 +01:00
irq-partition-percpu.h	irqchip: Add per-cpu interrupt partitioning library	2016-05-02 13:42:51 +02:00
irq-sa11x0.h	ARM: 8367/1: sa1100: prepare for moving irq driver to drivers/irqchip	2015-05-28 14:40:03 +01:00
metag-ext.h
metag.h
mips-gic.h	clocksource: Use a plain u64 instead of cycle_t	2016-12-25 11:04:12 +01:00
mmp.h
mxs.h
versatile-fpga.h
xtensa-mx.h	xtensa: add MX irqchip	2014-01-14 10:19:58 -08:00
xtensa-pic.h	xtensa: move built-in PIC to drivers/irqchip	2014-01-14 10:19:56 -08:00