mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 20:23:57 +08:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
416 lines
13 KiB
C
416 lines
13 KiB
C
/*
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* linux/arch/m68k/console/cvision.h -- CyberVision64 definitions for the
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* text console driver.
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*
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* Copyright (c) 1998 Alan Bair
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*
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* This file is based on the initial port to Linux of grf_cvreg.h:
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*
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* Copyright (c) 1997 Antonio Santos
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*
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* The original work is from the NetBSD CyberVision 64 framebuffer driver
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* and support files (grf_cv.c, grf_cvreg.h, ite_cv.c):
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* Permission to use the source of this driver was obtained from the
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* author Michael Teske by Alan Bair.
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*
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* Copyright (c) 1995 Michael Teske
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*
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* History:
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*
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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/* s3 commands */
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#define S3_BITBLT 0xc011
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#define S3_TWOPOINTLINE 0x2811
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#define S3_FILLEDRECT 0x40b1
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#define S3_FIFO_EMPTY 0x0400
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#define S3_HDW_BUSY 0x0200
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/* Enhanced register mapping (MMIO mode) */
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#define S3_READ_SEL 0xbee8 /* offset f */
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#define S3_MULT_MISC 0xbee8 /* offset e */
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#define S3_ERR_TERM 0x92e8
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#define S3_FRGD_COLOR 0xa6e8
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#define S3_BKGD_COLOR 0xa2e8
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#define S3_PIXEL_CNTL 0xbee8 /* offset a */
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#define S3_FRGD_MIX 0xbae8
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#define S3_BKGD_MIX 0xb6e8
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#define S3_CUR_Y 0x82e8
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#define S3_CUR_X 0x86e8
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#define S3_DESTY_AXSTP 0x8ae8
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#define S3_DESTX_DIASTP 0x8ee8
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#define S3_MIN_AXIS_PCNT 0xbee8 /* offset 0 */
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#define S3_MAJ_AXIS_PCNT 0x96e8
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#define S3_CMD 0x9ae8
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#define S3_GP_STAT 0x9ae8
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#define S3_ADVFUNC_CNTL 0x4ae8
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#define S3_WRT_MASK 0xaae8
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#define S3_RD_MASK 0xaee8
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/* Enhanced register mapping (Packed MMIO mode, write only) */
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#define S3_ALT_CURXY 0x8100
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#define S3_ALT_CURXY2 0x8104
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#define S3_ALT_STEP 0x8108
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#define S3_ALT_STEP2 0x810c
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#define S3_ALT_ERR 0x8110
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#define S3_ALT_CMD 0x8118
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#define S3_ALT_MIX 0x8134
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#define S3_ALT_PCNT 0x8148
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#define S3_ALT_PAT 0x8168
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/* Drawing modes */
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#define S3_NOTCUR 0x0000
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#define S3_LOGICALZERO 0x0001
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#define S3_LOGICALONE 0x0002
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#define S3_LEAVEASIS 0x0003
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#define S3_NOTNEW 0x0004
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#define S3_CURXORNEW 0x0005
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#define S3_NOT_CURXORNEW 0x0006
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#define S3_NEW 0x0007
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#define S3_NOTCURORNOTNEW 0x0008
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#define S3_CURORNOTNEW 0x0009
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#define S3_NOTCURORNEW 0x000a
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#define S3_CURORNEW 0x000b
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#define S3_CURANDNEW 0x000c
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#define S3_NOTCURANDNEW 0x000d
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#define S3_CURANDNOTNEW 0x000e
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#define S3_NOTCURANDNOTNEW 0x000f
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#define S3_CRTC_ADR 0x03d4
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#define S3_CRTC_DATA 0x03d5
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#define S3_REG_LOCK2 0x39
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#define S3_HGC_MODE 0x45
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#define S3_HWGC_ORGX_H 0x46
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#define S3_HWGC_ORGX_L 0x47
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#define S3_HWGC_ORGY_H 0x48
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#define S3_HWGC_ORGY_L 0x49
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#define S3_HWGC_DX 0x4e
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#define S3_HWGC_DY 0x4f
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#define S3_LAW_CTL 0x58
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/**************************************************/
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/* support for a BitBlt operation. The op-codes are identical
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to X11 GCs */
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#define GRFBBOPclear 0x0 /* 0 */
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#define GRFBBOPand 0x1 /* src AND dst */
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#define GRFBBOPandReverse 0x2 /* src AND NOT dst */
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#define GRFBBOPcopy 0x3 /* src */
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#define GRFBBOPandInverted 0x4 /* NOT src AND dst */
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#define GRFBBOPnoop 0x5 /* dst */
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#define GRFBBOPxor 0x6 /* src XOR dst */
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#define GRFBBOPor 0x7 /* src OR dst */
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#define GRFBBOPnor 0x8 /* NOT src AND NOT dst */
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#define GRFBBOPequiv 0x9 /* NOT src XOR dst */
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#define GRFBBOPinvert 0xa /* NOT dst */
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#define GRFBBOPorReverse 0xb /* src OR NOT dst */
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#define GRFBBOPcopyInverted 0xc /* NOT src */
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#define GRFBBOPorInverted 0xd /* NOT src OR dst */
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#define GRFBBOPnand 0xe /* NOT src OR NOT dst */
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#define GRFBBOPset 0xf /* 1 */
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/* Write 16 Bit VGA register */
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#define vgaw16(ba, reg, val) \
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*((unsigned short *) (((volatile unsigned char *)ba)+reg)) = val
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/*
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* Defines for the used register addresses (mw)
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*
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* NOTE: There are some registers that have different addresses when
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* in mono or color mode. We only support color mode, and thus
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* some addresses won't work in mono-mode!
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*
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* General and VGA-registers taken from retina driver. Fixed a few
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* bugs in it. (SR and GR read address is Port + 1, NOT Port)
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*
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*/
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/* General Registers: */
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#define GREG_MISC_OUTPUT_R 0x03CC
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#define GREG_MISC_OUTPUT_W 0x03C2
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#define GREG_FEATURE_CONTROL_R 0x03CA
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#define GREG_FEATURE_CONTROL_W 0x03DA
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#define GREG_INPUT_STATUS0_R 0x03C2
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#define GREG_INPUT_STATUS1_R 0x03DA
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/* Setup Registers: */
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#define SREG_OPTION_SELECT 0x0102
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#define SREG_VIDEO_SUBS_ENABLE 0x46E8
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/* Attribute Controller: */
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#define ACT_ADDRESS 0x03C0
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#define ACT_ADDRESS_R 0x03C1
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#define ACT_ADDRESS_W 0x03C0
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#define ACT_ADDRESS_RESET 0x03DA
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#define ACT_ID_PALETTE0 0x00
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#define ACT_ID_PALETTE1 0x01
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#define ACT_ID_PALETTE2 0x02
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#define ACT_ID_PALETTE3 0x03
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#define ACT_ID_PALETTE4 0x04
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#define ACT_ID_PALETTE5 0x05
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#define ACT_ID_PALETTE6 0x06
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#define ACT_ID_PALETTE7 0x07
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#define ACT_ID_PALETTE8 0x08
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#define ACT_ID_PALETTE9 0x09
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#define ACT_ID_PALETTE10 0x0A
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#define ACT_ID_PALETTE11 0x0B
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#define ACT_ID_PALETTE12 0x0C
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#define ACT_ID_PALETTE13 0x0D
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#define ACT_ID_PALETTE14 0x0E
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#define ACT_ID_PALETTE15 0x0F
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#define ACT_ID_ATTR_MODE_CNTL 0x10
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#define ACT_ID_OVERSCAN_COLOR 0x11
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#define ACT_ID_COLOR_PLANE_ENA 0x12
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#define ACT_ID_HOR_PEL_PANNING 0x13
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#define ACT_ID_COLOR_SELECT 0x14
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/* Graphics Controller: */
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#define GCT_ADDRESS 0x03CE
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#define GCT_ADDRESS_R 0x03CF
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#define GCT_ADDRESS_W 0x03CF
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#define GCT_ID_SET_RESET 0x00
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#define GCT_ID_ENABLE_SET_RESET 0x01
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#define GCT_ID_COLOR_COMPARE 0x02
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#define GCT_ID_DATA_ROTATE 0x03
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#define GCT_ID_READ_MAP_SELECT 0x04
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#define GCT_ID_GRAPHICS_MODE 0x05
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#define GCT_ID_MISC 0x06
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#define GCT_ID_COLOR_XCARE 0x07
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#define GCT_ID_BITMASK 0x08
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/* Sequencer: */
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#define SEQ_ADDRESS 0x03C4
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#define SEQ_ADDRESS_R 0x03C5
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#define SEQ_ADDRESS_W 0x03C5
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#define SEQ_ID_RESET 0x00
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#define SEQ_ID_CLOCKING_MODE 0x01
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#define SEQ_ID_MAP_MASK 0x02
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#define SEQ_ID_CHAR_MAP_SELECT 0x03
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#define SEQ_ID_MEMORY_MODE 0x04
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#define SEQ_ID_UNKNOWN1 0x05
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#define SEQ_ID_UNKNOWN2 0x06
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#define SEQ_ID_UNKNOWN3 0x07
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/* S3 extensions */
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#define SEQ_ID_UNLOCK_EXT 0x08
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#define SEQ_ID_EXT_SEQ_REG9 0x09
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#define SEQ_ID_BUS_REQ_CNTL 0x0A
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#define SEQ_ID_EXT_MISC_SEQ 0x0B
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#define SEQ_ID_UNKNOWN4 0x0C
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#define SEQ_ID_EXT_SEQ 0x0D
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#define SEQ_ID_UNKNOWN5 0x0E
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#define SEQ_ID_UNKNOWN6 0x0F
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#define SEQ_ID_MCLK_LO 0x10
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#define SEQ_ID_MCLK_HI 0x11
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#define SEQ_ID_DCLK_LO 0x12
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#define SEQ_ID_DCLK_HI 0x13
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#define SEQ_ID_CLKSYN_CNTL_1 0x14
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#define SEQ_ID_CLKSYN_CNTL_2 0x15
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#define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
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#define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
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#define SEQ_ID_RAMDAC_CNTL 0x18
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#define SEQ_ID_MORE_MAGIC 0x1A
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/* CRT Controller: */
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#define CRT_ADDRESS 0x03D4
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#define CRT_ADDRESS_R 0x03D5
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#define CRT_ADDRESS_W 0x03D5
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#define CRT_ID_HOR_TOTAL 0x00
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#define CRT_ID_HOR_DISP_ENA_END 0x01
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#define CRT_ID_START_HOR_BLANK 0x02
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#define CRT_ID_END_HOR_BLANK 0x03
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#define CRT_ID_START_HOR_RETR 0x04
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#define CRT_ID_END_HOR_RETR 0x05
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#define CRT_ID_VER_TOTAL 0x06
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#define CRT_ID_OVERFLOW 0x07
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#define CRT_ID_PRESET_ROW_SCAN 0x08
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#define CRT_ID_MAX_SCAN_LINE 0x09
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#define CRT_ID_CURSOR_START 0x0A
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#define CRT_ID_CURSOR_END 0x0B
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#define CRT_ID_START_ADDR_HIGH 0x0C
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#define CRT_ID_START_ADDR_LOW 0x0D
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#define CRT_ID_CURSOR_LOC_HIGH 0x0E
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#define CRT_ID_CURSOR_LOC_LOW 0x0F
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#define CRT_ID_START_VER_RETR 0x10
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#define CRT_ID_END_VER_RETR 0x11
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#define CRT_ID_VER_DISP_ENA_END 0x12
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#define CRT_ID_SCREEN_OFFSET 0x13
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#define CRT_ID_UNDERLINE_LOC 0x14
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#define CRT_ID_START_VER_BLANK 0x15
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#define CRT_ID_END_VER_BLANK 0x16
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#define CRT_ID_MODE_CONTROL 0x17
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#define CRT_ID_LINE_COMPARE 0x18
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#define CRT_ID_GD_LATCH_RBACK 0x22
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#define CRT_ID_ACT_TOGGLE_RBACK 0x24
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#define CRT_ID_ACT_INDEX_RBACK 0x26
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/* S3 extensions: S3 VGA Registers */
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#define CRT_ID_DEVICE_HIGH 0x2D
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#define CRT_ID_DEVICE_LOW 0x2E
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#define CRT_ID_REVISION 0x2F
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#define CRT_ID_CHIP_ID_REV 0x30
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#define CRT_ID_MEMORY_CONF 0x31
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#define CRT_ID_BACKWAD_COMP_1 0x32
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#define CRT_ID_BACKWAD_COMP_2 0x33
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#define CRT_ID_BACKWAD_COMP_3 0x34
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#define CRT_ID_REGISTER_LOCK 0x35
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#define CRT_ID_CONFIG_1 0x36
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#define CRT_ID_CONFIG_2 0x37
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#define CRT_ID_REGISTER_LOCK_1 0x38
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#define CRT_ID_REGISTER_LOCK_2 0x39
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#define CRT_ID_MISC_1 0x3A
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#define CRT_ID_DISPLAY_FIFO 0x3B
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#define CRT_ID_LACE_RETR_START 0x3C
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/* S3 extensions: System Control Registers */
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#define CRT_ID_SYSTEM_CONFIG 0x40
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#define CRT_ID_BIOS_FLAG 0x41
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#define CRT_ID_LACE_CONTROL 0x42
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#define CRT_ID_EXT_MODE 0x43
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#define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
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#define CRT_ID_HWGC_ORIGIN_X_HI 0x46
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#define CRT_ID_HWGC_ORIGIN_X_LO 0x47
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#define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
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#define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
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#define CRT_ID_HWGC_FG_STACK 0x4A
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#define CRT_ID_HWGC_BG_STACK 0x4B
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#define CRT_ID_HWGC_START_AD_HI 0x4C
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#define CRT_ID_HWGC_START_AD_LO 0x4D
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#define CRT_ID_HWGC_DSTART_X 0x4E
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#define CRT_ID_HWGC_DSTART_Y 0x4F
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/* S3 extensions: System Extension Registers */
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#define CRT_ID_EXT_SYS_CNTL_1 0x50
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#define CRT_ID_EXT_SYS_CNTL_2 0x51
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#define CRT_ID_EXT_BIOS_FLAG_1 0x52
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#define CRT_ID_EXT_MEM_CNTL_1 0x53
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#define CRT_ID_EXT_MEM_CNTL_2 0x54
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#define CRT_ID_EXT_DAC_CNTL 0x55
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#define CRT_ID_EX_SYNC_1 0x56
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#define CRT_ID_EX_SYNC_2 0x57
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#define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
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#define CRT_ID_LAW_POS_HI 0x59
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#define CRT_ID_LAW_POS_LO 0x5A
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#define CRT_ID_GOUT_PORT 0x5C
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#define CRT_ID_EXT_HOR_OVF 0x5D
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#define CRT_ID_EXT_VER_OVF 0x5E
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#define CRT_ID_EXT_MEM_CNTL_3 0x60
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#define CRT_ID_EX_SYNC_3 0x63
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#define CRT_ID_EXT_MISC_CNTL 0x65
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#define CRT_ID_EXT_MISC_CNTL_1 0x66
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#define CRT_ID_EXT_MISC_CNTL_2 0x67
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#define CRT_ID_CONFIG_3 0x68
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#define CRT_ID_EXT_SYS_CNTL_3 0x69
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#define CRT_ID_EXT_SYS_CNTL_4 0x6A
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#define CRT_ID_EXT_BIOS_FLAG_3 0x6B
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#define CRT_ID_EXT_BIOS_FLAG_4 0x6C
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/* Enhanced Commands Registers: */
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#define ECR_SUBSYSTEM_STAT 0x42E8
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#define ECR_SUBSYSTEM_CNTL 0x42E8
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#define ECR_ADV_FUNC_CNTL 0x4AE8
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#define ECR_CURRENT_Y_POS 0x82E8
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#define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */
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#define ECR_CURRENT_X_POS 0x86E8
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#define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */
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#define ECR_DEST_Y__AX_STEP 0x8AE8
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#define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */
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#define ECR_DEST_X__DIA_STEP 0x8EE8
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#define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */
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#define ECR_ERR_TERM 0x92E8
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#define ECR_ERR_TERM2 0x92EA /* Trio64 only */
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#define ECR_MAJ_AXIS_PIX_CNT 0x96E8
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#define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */
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#define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */
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#define ECR_DRAW_CMD 0x9AE8
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#define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */
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#define ECR_SHORT_STROKE 0x9EE8
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#define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */
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#define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */
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#define ECR_BITPLANE_WRITE_MASK 0xAAE8
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#define ECR_BITPLANE_READ_MASK 0xAEE8
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#define ECR_COLOR_COMPARE 0xB2E8
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#define ECR_BKGD_MIX 0xB6E8
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#define ECR_FRGD_MIX 0xBAE8
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#define ECR_READ_REG_DATA 0xBEE8
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#define ECR_ID_MIN_AXIS_PIX_CNT 0x00
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#define ECR_ID_SCISSORS_TOP 0x01
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#define ECR_ID_SCISSORS_LEFT 0x02
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#define ECR_ID_SCISSORS_BUTTOM 0x03
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#define ECR_ID_SCISSORS_RIGHT 0x04
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#define ECR_ID_PIX_CNTL 0x0A
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#define ECR_ID_MULT_CNTL_MISC_2 0x0D
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#define ECR_ID_MULT_CNTL_MISC 0x0E
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#define ECR_ID_READ_SEL 0x0F
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#define ECR_PIX_TRANS 0xE2E8
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#define ECR_PIX_TRANS_EXT 0xE2EA
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#define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */
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#define ECR_PATTERN_X 0xEAEA /* Trio64 only */
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/* Pass-through */
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#define PASS_ADDRESS 0x40001
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#define PASS_ADDRESS_W 0x40001
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/* Video DAC */
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#define VDAC_ADDRESS 0x03c8
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#define VDAC_ADDRESS_W 0x03c8
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#define VDAC_ADDRESS_R 0x03c7
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#define VDAC_STATE 0x03c7
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#define VDAC_DATA 0x03c9
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#define VDAC_MASK 0x03c6
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#define WGfx(ba, idx, val) \
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do { wb_64(ba, GCT_ADDRESS, idx); wb_64(ba, GCT_ADDRESS_W , val); } while (0)
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#define WSeq(ba, idx, val) \
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do { wb_64(ba, SEQ_ADDRESS, idx); wb_64(ba, SEQ_ADDRESS_W , val); } while (0)
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#define WCrt(ba, idx, val) \
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do { wb_64(ba, CRT_ADDRESS, idx); wb_64(ba, CRT_ADDRESS_W , val); } while (0)
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#define WAttr(ba, idx, val) \
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do { \
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unsigned char tmp;\
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tmp = rb_64(ba, ACT_ADDRESS_RESET);\
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wb_64(ba, ACT_ADDRESS_W, idx);\
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wb_64(ba, ACT_ADDRESS_W, val);\
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} while (0)
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#define SetTextPlane(ba, m) \
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do { \
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WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
|
|
WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
|
|
} while (0)
|
|
|
|
/* --------------------------------- */
|
|
/* prototypes */
|
|
/* --------------------------------- */
|
|
|
|
inline unsigned char RAttr(volatile unsigned char * board, short idx);
|
|
inline unsigned char RSeq(volatile unsigned char * board, short idx);
|
|
inline unsigned char RCrt(volatile unsigned char * board, short idx);
|
|
inline unsigned char RGfx(volatile unsigned char * board, short idx);
|
|
inline void cv64_write_port(unsigned short bits,
|
|
volatile unsigned char *board);
|
|
inline void cvscreen(int toggle, volatile unsigned char *board);
|
|
inline void gfx_on_off(int toggle, volatile unsigned char *board);
|
|
#if 0
|
|
unsigned short cv64_compute_clock(unsigned long freq);
|
|
int cv_has_4mb(volatile unsigned char * fb);
|
|
void cv64_board_init(void);
|
|
void cv64_load_video_mode(struct fb_var_screeninfo *video_mode);
|
|
#endif
|
|
|
|
void cvision_bitblt(u_short sx, u_short sy, u_short dx, u_short dy, u_short w,
|
|
u_short h);
|
|
void cvision_clear(u_short dx, u_short dy, u_short w, u_short h, u_short bg);
|