mirror of
https://github.com/edk2-porting/linux-next.git
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a36cf68651
Core changes: * Support non-uniform erase size * Support controllers with limited TX fifo size Driver changes: * m25p80: Re-issue a WREN command after each write access * cadence: Pass a proper dir value to dma_[un]map_single() * fsl-qspi: Check fsl_qspi_get_seqid() return val make sure 4B addressing opcodes are properly handled * intel-spi: Add a new PCI entry for Ice Lake NAND changes: Raw NAND core changes: - Two batchs of cleanups of the NAND API, including: * Deprecating a lot of interfaces (now replaced by ->exec_op()). * Moving code in separate drivers (JEDEC, ONFI), in private files (internals), in platform drivers, etc. * Functions/structures reordering. * Exclusive use of the nand_chip structure instead of the MTD one all across the subsystem. - Addition of the nand_wait_readrdy/rdy_op() helpers. Raw NAND controllers drivers changes: - Various coccinelle patches. - Marvell: * Use regmap_update_bits() for syscon access. * More documentation. * BCH failure path rework. * More layouts to be supported. * IRQ handler complete() condition fixed. - Fsl_ifc: * SRAM initialization fixed for newer controller versions. - Denali: * Fix licenses mismatch and use a SPDX tag. * Set SPARE_AREA_SKIP_BYTES register to 8 if unset. - Qualcomm: * Do not include dma-direct.h. - Docg4: * Removed. - Ams-delta: * Use of a GPIO lookup table * Internal machinery changes. Raw NAND chip drivers changes: - Toshiba: * Add support for Toshiba memory BENAND * Pass a single nand_chip object to the status helper. - ESMT: * New driver to retrieve the ECC requirements from the 5th ID byte. MTD changes: * physmap cleanups/fixe * gpio-addr-flash cleanups/fixes -----BEGIN PGP SIGNATURE----- iQJQBAABCgA6FiEEKmCqpbOU668PNA69Ze02AX4ItwAFAlvNmJocHGJvcmlzLmJy ZXppbGxvbkBib290bGluLmNvbQAKCRBl7TYBfgi3AKr+D/4pH0gYSGDUstZsqUHW gZsPRU4jmOA+OCRbSxE03bOZOYR0UPgdoUYLfAKhZ5qxc7wHd3b47wykP0kUEviu lC8QhSs4DUA+EuMVPDVS4FlXRT0e3dMV7jh/IK6nInshD2YkaovyCqa6GvgwFEcM 7BCizxRhtHV8+fo7GVQWuMLb9ZfbEvz42D0sYOu6hIsF1SnRDvHOvfdDUFEXpJoF a2mC9ove65ChEzc2iZ/r260iZ4aoJYb9XJRJKWxmYeITZSmLNmcrUyGqAaNQ7NRc AIuPXASbeHGjrIuEfXpKYW07AE5MV1nJFSk3v4u5FjgoohOoobPp7npk+Lz/qwe3 y8/uW9qOQ/iEOsRnkvMGNu4Yjhw41L1a+J5wVvUvzmwHy1xMCrRHYB/8gXoZzemR A7XmCPwjAFVWv1WeKV2cs5MLW9yZq9QNMtGLlNs5OgFR6CccLk67/tHIkYLsJ/l9 IDXFhd/YKhTeF361u6Iimmgb427TwM71P9N+OMpv4nk46DxurpxkgGle3nslzKNU DOFNFlMGiPIx3h4X96AKER6u7cxiOXnLGq+XeHa/y8tIrziy3jg03YoTh0RSwKxV J3EXwh1sFLaeebwWEgpE3Ag1LOxpRCqJ2ED71SPzS/DR/938HBVsEoPqUEHNf1in jwsUB3cRzNwf+XX68DRCVT5GFA== =7w4w -----END PGP SIGNATURE----- Merge tag 'mtd/for-4.20' of git://git.infradead.org/linux-mtd Pull mtd updates from Boris Brezillon: "SPI NOR core changes: - Support non-uniform erase size - Support controllers with limited TX fifo size Driver changes: - m25p80: Re-issue a WREN command after each write access - cadence: Pass a proper dir value to dma_[un]map_single() - fsl-qspi: Check fsl_qspi_get_seqid() return val make sure 4B addressing opcodes are properly handled - intel-spi: Add a new PCI entry for Ice Lake Raw NAND core changes: - Two batchs of cleanups of the NAND API, including: * Deprecating a lot of interfaces (now replaced by ->exec_op()). * Moving code in separate drivers (JEDEC, ONFI), in private files (internals), in platform drivers, etc. * Functions/structures reordering. * Exclusive use of the nand_chip structure instead of the MTD one all across the subsystem. - Addition of the nand_wait_readrdy/rdy_op() helpers. Raw NAND controllers drivers changes: - Various coccinelle patches. - Marvell: * Use regmap_update_bits() for syscon access. * More documentation. * BCH failure path rework. * More layouts to be supported. * IRQ handler complete() condition fixed. - Fsl_ifc: * SRAM initialization fixed for newer controller versions. - Denali: * Fix licenses mismatch and use a SPDX tag. * Set SPARE_AREA_SKIP_BYTES register to 8 if unset. - Qualcomm: * Do not include dma-direct.h. - Docg4: * Removed. - Ams-delta: * Use of a GPIO lookup table * Internal machinery changes. Raw NAND chip drivers changes: - Toshiba: * Add support for Toshiba memory BENAND * Pass a single nand_chip object to the status helper. - ESMT: * New driver to retrieve the ECC requirements from the 5th ID byte. MTD changes: - physmap cleanups/fixe - gpio-addr-flash cleanups/fixes" * tag 'mtd/for-4.20' of git://git.infradead.org/linux-mtd: (93 commits) jffs2: free jffs2_sb_info through jffs2_kill_sb() mtd: spi-nor: fsl-quadspi: fix read error for flash size larger than 16MB mtd: spi-nor: intel-spi: Add support for Intel Ice Lake SPI serial flash mtd: maps: gpio-addr-flash: Convert to gpiod mtd: maps: gpio-addr-flash: Replace array with an integer mtd: maps: gpio-addr-flash: Use order instead of size mtd: spi-nor: fsl-quadspi: Don't let -EINVAL on the bus mtd: devices: m25p80: Make sure WRITE_EN is issued before each write mtd: spi-nor: Support controllers with limited TX FIFO size mtd: spi-nor: cadence-quadspi: Use proper enum for dma_[un]map_single mtd: spi-nor: parse SFDP Sector Map Parameter Table mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories mtd: rawnand: marvell: fix the IRQ handler complete() condition mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES register to 8 if unset mtd: rawnand: r852: fix spelling mistake "card_registred" -> "card_registered" mtd: rawnand: toshiba: Pass a single nand_chip object to the status helper mtd: maps: gpio-addr-flash: Use devm_* functions mtd: maps: gpio-addr-flash: Fix ioremapped size mtd: maps: gpio-addr-flash: Replace custom printk mtd: physmap_of: Release resources on error ...
345 lines
9.3 KiB
C
345 lines
9.3 KiB
C
/*
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* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
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*
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* Author: Mike Lavender, mike@steroidmicros.com
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*
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* Copyright (c) 2005, Intec Automation Inc.
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*
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* Some parts are based on lart.c by Abraham Van Der Merwe
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*
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* Cleaned up and generalized based on mtd_dataflash.c
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/spi-nor.h>
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struct m25p {
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struct spi_mem *spimem;
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struct spi_nor spi_nor;
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};
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static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
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{
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struct m25p *flash = nor->priv;
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(len, NULL, 1));
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void *scratchbuf;
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int ret;
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scratchbuf = kmalloc(len, GFP_KERNEL);
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if (!scratchbuf)
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return -ENOMEM;
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op.data.buf.in = scratchbuf;
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ret = spi_mem_exec_op(flash->spimem, &op);
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if (ret < 0)
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dev_err(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
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code);
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else
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memcpy(val, scratchbuf, len);
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kfree(scratchbuf);
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return ret;
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}
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static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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struct m25p *flash = nor->priv;
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(len, NULL, 1));
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void *scratchbuf;
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int ret;
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scratchbuf = kmemdup(buf, len, GFP_KERNEL);
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if (!scratchbuf)
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return -ENOMEM;
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op.data.buf.out = scratchbuf;
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ret = spi_mem_exec_op(flash->spimem, &op);
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kfree(scratchbuf);
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return ret;
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}
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static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
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const u_char *buf)
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{
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struct m25p *flash = nor->priv;
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
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SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(len, buf, 1));
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int ret;
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/* get transfer protocols. */
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op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
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op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
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op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
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if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
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op.addr.nbytes = 0;
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ret = spi_mem_adjust_op_size(flash->spimem, &op);
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if (ret)
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return ret;
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op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
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ret = spi_mem_exec_op(flash->spimem, &op);
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if (ret)
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return ret;
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return op.data.nbytes;
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}
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/*
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* Read an address range from the nor chip. The address range
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* may be any size provided it is within the physical boundaries.
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*/
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static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
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u_char *buf)
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{
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struct m25p *flash = nor->priv;
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
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SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
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SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
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SPI_MEM_OP_DATA_IN(len, buf, 1));
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size_t remaining = len;
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int ret;
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/* get transfer protocols. */
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op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
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op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
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op.dummy.buswidth = op.addr.buswidth;
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op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
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/* convert the dummy cycles to the number of bytes */
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op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
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while (remaining) {
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op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
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ret = spi_mem_adjust_op_size(flash->spimem, &op);
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if (ret)
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return ret;
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ret = spi_mem_exec_op(flash->spimem, &op);
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if (ret)
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return ret;
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op.addr.val += op.data.nbytes;
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remaining -= op.data.nbytes;
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op.data.buf.in += op.data.nbytes;
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}
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return len;
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}
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/*
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* board specific setup should have ensured the SPI clock used here
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* matches what the READ command supports, at least until this driver
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* understands FAST_READ (for clocks over 25 MHz).
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*/
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static int m25p_probe(struct spi_mem *spimem)
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{
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struct spi_device *spi = spimem->spi;
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struct flash_platform_data *data;
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struct m25p *flash;
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struct spi_nor *nor;
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struct spi_nor_hwcaps hwcaps = {
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.mask = SNOR_HWCAPS_READ |
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SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_PP,
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};
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char *flash_name;
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int ret;
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data = dev_get_platdata(&spimem->spi->dev);
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flash = devm_kzalloc(&spimem->spi->dev, sizeof(*flash), GFP_KERNEL);
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if (!flash)
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return -ENOMEM;
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nor = &flash->spi_nor;
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/* install the hooks */
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nor->read = m25p80_read;
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nor->write = m25p80_write;
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nor->write_reg = m25p80_write_reg;
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nor->read_reg = m25p80_read_reg;
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nor->dev = &spimem->spi->dev;
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spi_nor_set_flash_node(nor, spi->dev.of_node);
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nor->priv = flash;
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spi_mem_set_drvdata(spimem, flash);
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flash->spimem = spimem;
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if (spi->mode & SPI_RX_QUAD) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
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if (spi->mode & SPI_TX_QUAD)
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hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
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SNOR_HWCAPS_PP_1_1_4 |
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SNOR_HWCAPS_PP_1_4_4);
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} else if (spi->mode & SPI_RX_DUAL) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
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if (spi->mode & SPI_TX_DUAL)
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hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
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}
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if (data && data->name)
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nor->mtd.name = data->name;
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if (!nor->mtd.name)
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nor->mtd.name = spi_mem_get_name(spimem);
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/* For some (historical?) reason many platforms provide two different
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* names in flash_platform_data: "name" and "type". Quite often name is
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* set to "m25p80" and then "type" provides a real chip name.
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* If that's the case, respect "type" and ignore a "name".
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*/
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if (data && data->type)
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flash_name = data->type;
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else if (!strcmp(spi->modalias, "spi-nor"))
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flash_name = NULL; /* auto-detect */
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else
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flash_name = spi->modalias;
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ret = spi_nor_scan(nor, flash_name, &hwcaps);
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if (ret)
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return ret;
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return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
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data ? data->nr_parts : 0);
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}
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static int m25p_remove(struct spi_mem *spimem)
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{
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struct m25p *flash = spi_mem_get_drvdata(spimem);
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spi_nor_restore(&flash->spi_nor);
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/* Clean up MTD stuff. */
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return mtd_device_unregister(&flash->spi_nor.mtd);
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}
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static void m25p_shutdown(struct spi_mem *spimem)
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{
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struct m25p *flash = spi_mem_get_drvdata(spimem);
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spi_nor_restore(&flash->spi_nor);
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}
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/*
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* Do NOT add to this array without reading the following:
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*
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* Historically, many flash devices are bound to this driver by their name. But
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* since most of these flash are compatible to some extent, and their
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* differences can often be differentiated by the JEDEC read-ID command, we
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* encourage new users to add support to the spi-nor library, and simply bind
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* against a generic string here (e.g., "jedec,spi-nor").
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*
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* Many flash names are kept here in this list (as well as in spi-nor.c) to
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* keep them available as module aliases for existing platforms.
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*/
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static const struct spi_device_id m25p_ids[] = {
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/*
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* Allow non-DT platform devices to bind to the "spi-nor" modalias, and
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* hack around the fact that the SPI core does not provide uevent
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* matching for .of_match_table
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*/
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{"spi-nor"},
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/*
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* Entries not used in DTs that should be safe to drop after replacing
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* them with "spi-nor" in platform data.
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*/
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{"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
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/*
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* Entries that were used in DTs without "jedec,spi-nor" fallback and
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* should be kept for backward compatibility.
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*/
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{"at25df321a"}, {"at25df641"}, {"at26df081a"},
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{"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
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{"mx25l25635e"},{"mx66l51235l"},
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{"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
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{"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
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{"s25fl064k"},
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{"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
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{"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
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{"m25p64"}, {"m25p128"},
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{"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
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{"w25q80bl"}, {"w25q128"}, {"w25q256"},
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/* Flashes that can't be detected using JEDEC */
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{"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
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{"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
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{"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
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/* Everspin MRAMs (non-JEDEC) */
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{ "mr25h128" }, /* 128 Kib, 40 MHz */
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{ "mr25h256" }, /* 256 Kib, 40 MHz */
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{ "mr25h10" }, /* 1 Mib, 40 MHz */
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{ "mr25h40" }, /* 4 Mib, 40 MHz */
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{ },
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};
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MODULE_DEVICE_TABLE(spi, m25p_ids);
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static const struct of_device_id m25p_of_table[] = {
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/*
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* Generic compatibility for SPI NOR that can be identified by the
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* JEDEC READ ID opcode (0x9F). Use this, if possible.
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*/
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{ .compatible = "jedec,spi-nor" },
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{}
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};
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MODULE_DEVICE_TABLE(of, m25p_of_table);
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static struct spi_mem_driver m25p80_driver = {
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.spidrv = {
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.driver = {
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.name = "m25p80",
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.of_match_table = m25p_of_table,
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},
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.id_table = m25p_ids,
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},
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.probe = m25p_probe,
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.remove = m25p_remove,
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.shutdown = m25p_shutdown,
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/* REVISIT: many of these chips have deep power-down modes, which
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* should clearly be entered on suspend() to minimize power use.
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* And also when they're otherwise idle...
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*/
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};
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module_spi_mem_driver(m25p80_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Mike Lavender");
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MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
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