mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 05:04:00 +08:00
524353ea48
The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
|
/*
|
|
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
|
|
#define _DT_BINDINGS_RESET_SUN50I_H6_H_
|
|
|
|
#define RST_MBUS 0
|
|
#define RST_BUS_DE 1
|
|
#define RST_BUS_DEINTERLACE 2
|
|
#define RST_BUS_GPU 3
|
|
#define RST_BUS_CE 4
|
|
#define RST_BUS_VE 5
|
|
#define RST_BUS_EMCE 6
|
|
#define RST_BUS_VP9 7
|
|
#define RST_BUS_DMA 8
|
|
#define RST_BUS_MSGBOX 9
|
|
#define RST_BUS_SPINLOCK 10
|
|
#define RST_BUS_HSTIMER 11
|
|
#define RST_BUS_DBG 12
|
|
#define RST_BUS_PSI 13
|
|
#define RST_BUS_PWM 14
|
|
#define RST_BUS_IOMMU 15
|
|
#define RST_BUS_DRAM 16
|
|
#define RST_BUS_NAND 17
|
|
#define RST_BUS_MMC0 18
|
|
#define RST_BUS_MMC1 19
|
|
#define RST_BUS_MMC2 20
|
|
#define RST_BUS_UART0 21
|
|
#define RST_BUS_UART1 22
|
|
#define RST_BUS_UART2 23
|
|
#define RST_BUS_UART3 24
|
|
#define RST_BUS_I2C0 25
|
|
#define RST_BUS_I2C1 26
|
|
#define RST_BUS_I2C2 27
|
|
#define RST_BUS_I2C3 28
|
|
#define RST_BUS_SCR0 29
|
|
#define RST_BUS_SCR1 30
|
|
#define RST_BUS_SPI0 31
|
|
#define RST_BUS_SPI1 32
|
|
#define RST_BUS_EMAC 33
|
|
#define RST_BUS_TS 34
|
|
#define RST_BUS_IR_TX 35
|
|
#define RST_BUS_THS 36
|
|
#define RST_BUS_I2S0 37
|
|
#define RST_BUS_I2S1 38
|
|
#define RST_BUS_I2S2 39
|
|
#define RST_BUS_I2S3 40
|
|
#define RST_BUS_SPDIF 41
|
|
#define RST_BUS_DMIC 42
|
|
#define RST_BUS_AUDIO_HUB 43
|
|
#define RST_USB_PHY0 44
|
|
#define RST_USB_PHY1 45
|
|
#define RST_USB_PHY3 46
|
|
#define RST_USB_HSIC 47
|
|
#define RST_BUS_OHCI0 48
|
|
#define RST_BUS_OHCI3 49
|
|
#define RST_BUS_EHCI0 50
|
|
#define RST_BUS_XHCI 51
|
|
#define RST_BUS_EHCI3 52
|
|
#define RST_BUS_OTG 53
|
|
#define RST_BUS_PCIE 54
|
|
#define RST_PCIE_POWERUP 55
|
|
#define RST_BUS_HDMI 56
|
|
#define RST_BUS_HDMI_SUB 57
|
|
#define RST_BUS_TCON_TOP 58
|
|
#define RST_BUS_TCON_LCD0 59
|
|
#define RST_BUS_TCON_TV0 60
|
|
#define RST_BUS_CSI 61
|
|
#define RST_BUS_HDCP 62
|
|
|
|
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
|