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87a3d523b3
Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SC7280 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1612981579-17391-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
227 lines
8.0 KiB
C
227 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H
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/* GCC clocks */
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#define GCC_GPLL0 0
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#define GCC_GPLL0_OUT_EVEN 1
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#define GCC_GPLL0_OUT_ODD 2
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#define GCC_GPLL1 3
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#define GCC_GPLL10 4
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#define GCC_GPLL4 5
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#define GCC_GPLL9 6
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#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 7
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#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 8
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 9
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10
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#define GCC_CAMERA_AHB_CLK 11
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#define GCC_CAMERA_HF_AXI_CLK 12
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#define GCC_CAMERA_SF_AXI_CLK 13
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#define GCC_CAMERA_XO_CLK 14
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 15
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 16
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#define GCC_CPUSS_AHB_CLK 17
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#define GCC_CPUSS_AHB_CLK_SRC 18
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 19
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#define GCC_DDRSS_GPU_AXI_CLK 20
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#define GCC_DDRSS_PCIE_SF_CLK 21
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#define GCC_DISP_AHB_CLK 22
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#define GCC_DISP_GPLL0_CLK_SRC 23
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#define GCC_DISP_HF_AXI_CLK 24
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#define GCC_DISP_SF_AXI_CLK 25
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#define GCC_DISP_XO_CLK 26
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#define GCC_GP1_CLK 27
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#define GCC_GP1_CLK_SRC 28
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#define GCC_GP2_CLK 29
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#define GCC_GP2_CLK_SRC 30
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#define GCC_GP3_CLK 31
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#define GCC_GP3_CLK_SRC 32
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#define GCC_GPU_CFG_AHB_CLK 33
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#define GCC_GPU_GPLL0_CLK_SRC 34
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
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#define GCC_GPU_IREF_EN 36
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#define GCC_GPU_MEMNOC_GFX_CLK 37
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#define GCC_GPU_SNOC_DVM_GFX_CLK 38
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#define GCC_PCIE0_PHY_RCHNG_CLK 39
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#define GCC_PCIE1_PHY_RCHNG_CLK 40
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#define GCC_PCIE_0_AUX_CLK 41
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#define GCC_PCIE_0_AUX_CLK_SRC 42
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#define GCC_PCIE_0_CFG_AHB_CLK 43
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#define GCC_PCIE_0_MSTR_AXI_CLK 44
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45
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#define GCC_PCIE_0_PIPE_CLK 46
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#define GCC_PCIE_0_PIPE_CLK_SRC 47
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#define GCC_PCIE_0_SLV_AXI_CLK 48
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
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#define GCC_PCIE_1_AUX_CLK 50
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#define GCC_PCIE_1_AUX_CLK_SRC 51
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#define GCC_PCIE_1_CFG_AHB_CLK 52
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#define GCC_PCIE_1_MSTR_AXI_CLK 53
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54
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#define GCC_PCIE_1_PIPE_CLK 55
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#define GCC_PCIE_1_PIPE_CLK_SRC 56
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#define GCC_PCIE_1_SLV_AXI_CLK 57
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58
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#define GCC_PCIE_THROTTLE_CORE_CLK 59
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#define GCC_PDM2_CLK 60
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#define GCC_PDM2_CLK_SRC 61
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#define GCC_PDM_AHB_CLK 62
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#define GCC_PDM_XO4_CLK 63
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 64
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 65
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#define GCC_QMIP_DISP_AHB_CLK 66
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 68
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#define GCC_QUPV3_WRAP0_CORE_CLK 69
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#define GCC_QUPV3_WRAP0_S0_CLK 70
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 71
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#define GCC_QUPV3_WRAP0_S1_CLK 72
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 73
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#define GCC_QUPV3_WRAP0_S2_CLK 74
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 75
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#define GCC_QUPV3_WRAP0_S3_CLK 76
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 77
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#define GCC_QUPV3_WRAP0_S4_CLK 78
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 79
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#define GCC_QUPV3_WRAP0_S5_CLK 80
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 81
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#define GCC_QUPV3_WRAP0_S6_CLK 82
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 83
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#define GCC_QUPV3_WRAP0_S7_CLK 84
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 85
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 86
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#define GCC_QUPV3_WRAP1_CORE_CLK 87
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#define GCC_QUPV3_WRAP1_S0_CLK 88
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 89
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#define GCC_QUPV3_WRAP1_S1_CLK 90
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 91
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#define GCC_QUPV3_WRAP1_S2_CLK 92
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 93
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#define GCC_QUPV3_WRAP1_S3_CLK 94
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 95
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#define GCC_QUPV3_WRAP1_S4_CLK 96
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 97
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#define GCC_QUPV3_WRAP1_S5_CLK 98
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 99
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#define GCC_QUPV3_WRAP1_S6_CLK 100
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 101
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#define GCC_QUPV3_WRAP1_S7_CLK 102
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 103
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 104
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 105
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 106
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 107
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#define GCC_SDCC1_AHB_CLK 108
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#define GCC_SDCC1_APPS_CLK 109
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#define GCC_SDCC1_APPS_CLK_SRC 110
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#define GCC_SDCC1_ICE_CORE_CLK 111
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 112
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#define GCC_SDCC2_AHB_CLK 113
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#define GCC_SDCC2_APPS_CLK 114
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#define GCC_SDCC2_APPS_CLK_SRC 115
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#define GCC_SDCC4_AHB_CLK 116
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#define GCC_SDCC4_APPS_CLK 117
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#define GCC_SDCC4_APPS_CLK_SRC 118
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 119
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#define GCC_THROTTLE_PCIE_AHB_CLK 120
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#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 121
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#define GCC_TITAN_RT_THROTTLE_CORE_CLK 122
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#define GCC_UFS_1_CLKREF_EN 123
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#define GCC_UFS_PHY_AHB_CLK 124
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#define GCC_UFS_PHY_AXI_CLK 125
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#define GCC_UFS_PHY_AXI_CLK_SRC 126
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#define GCC_UFS_PHY_ICE_CORE_CLK 127
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 128
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#define GCC_UFS_PHY_PHY_AUX_CLK 129
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 130
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 131
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 132
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 133
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 134
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 135
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 136
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 137
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138
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#define GCC_USB30_PRIM_MASTER_CLK 139
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 140
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 141
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 142
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 143
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#define GCC_USB30_PRIM_SLEEP_CLK 144
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#define GCC_USB30_SEC_MASTER_CLK 145
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#define GCC_USB30_SEC_MASTER_CLK_SRC 146
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 147
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 148
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 149
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#define GCC_USB30_SEC_SLEEP_CLK 150
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#define GCC_USB3_PRIM_PHY_AUX_CLK 151
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 154
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 155
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#define GCC_USB3_SEC_PHY_AUX_CLK 156
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 157
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 158
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#define GCC_USB3_SEC_PHY_PIPE_CLK 159
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 160
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#define GCC_VIDEO_AHB_CLK 161
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#define GCC_VIDEO_AXI0_CLK 162
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#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 163
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#define GCC_VIDEO_XO_CLK 164
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#define GCC_GPLL0_MAIN_DIV_CDIV 165
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 166
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#define GCC_QSPI_CORE_CLK 167
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#define GCC_QSPI_CORE_CLK_SRC 168
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#define GCC_CFG_NOC_LPASS_CLK 169
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#define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC 170
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#define GCC_MSS_CFG_AHB_CLK 171
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#define GCC_MSS_OFFLINE_AXI_CLK 172
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#define GCC_MSS_SNOC_AXI_CLK 173
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#define GCC_MSS_Q6_MEMNOC_AXI_CLK 174
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#define GCC_MSS_Q6SS_BOOT_CLK_SRC 175
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 176
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 177
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#define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 178
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#define GCC_PCIE_CLKREF_EN 179
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#define GCC_WPSS_AHB_CLK 180
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#define GCC_WPSS_AHB_BDG_MST_CLK 181
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#define GCC_WPSS_RSCP_CLK 182
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#define GCC_EDP_CLKREF_EN 183
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#define GCC_SEC_CTRL_CLK_SRC 184
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/* GCC power domains */
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#define GCC_PCIE_0_GDSC 0
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#define GCC_PCIE_1_GDSC 1
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#define GCC_UFS_PHY_GDSC 2
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#define GCC_USB30_PRIM_GDSC 3
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#define GCC_USB30_SEC_GDSC 4
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 5
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 6
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#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 7
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#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8
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#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9
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/* GCC resets */
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#define GCC_PCIE_0_BCR 0
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#define GCC_PCIE_0_PHY_BCR 1
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#define GCC_PCIE_1_BCR 2
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#define GCC_PCIE_1_PHY_BCR 3
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#define GCC_QUSB2PHY_PRIM_BCR 4
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#define GCC_QUSB2PHY_SEC_BCR 5
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#define GCC_SDCC1_BCR 6
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#define GCC_SDCC2_BCR 7
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#define GCC_SDCC4_BCR 8
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#define GCC_UFS_PHY_BCR 9
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#define GCC_USB30_PRIM_BCR 10
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#define GCC_USB30_SEC_BCR 11
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#define GCC_USB3_DP_PHY_PRIM_BCR 12
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#define GCC_USB3_PHY_PRIM_BCR 13
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#define GCC_USB3PHY_PHY_PRIM_BCR 14
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15
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#endif
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