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189 lines
5.8 KiB
C
189 lines
5.8 KiB
C
/*
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* o2micro.h 1.13 1999/10/25 20:03:34
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*
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* The contents of this file are subject to the Mozilla Public License
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* Version 1.1 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License
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* at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and
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* limitations under the License.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* Alternatively, the contents of this file may be used under the
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* terms of the GNU General Public License version 2 (the "GPL"), in which
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* case the provisions of the GPL are applicable instead of the
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* above. If you wish to allow the use of your version of this file
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* only under the terms of the GPL and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the GPL. If you do not delete the
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* provisions above, a recipient may use your version of this file
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* under either the MPL or the GPL.
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*/
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#ifndef _LINUX_O2MICRO_H
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#define _LINUX_O2MICRO_H
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#ifndef PCI_VENDOR_ID_O2
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#define PCI_VENDOR_ID_O2 0x1217
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#endif
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#ifndef PCI_DEVICE_ID_O2_6729
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#define PCI_DEVICE_ID_O2_6729 0x6729
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#endif
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#ifndef PCI_DEVICE_ID_O2_6730
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#define PCI_DEVICE_ID_O2_6730 0x673a
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#endif
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#ifndef PCI_DEVICE_ID_O2_6832
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#define PCI_DEVICE_ID_O2_6832 0x6832
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#endif
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#ifndef PCI_DEVICE_ID_O2_6836
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#define PCI_DEVICE_ID_O2_6836 0x6836
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#endif
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#ifndef PCI_DEVICE_ID_O2_6812
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#define PCI_DEVICE_ID_O2_6812 0x6872
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#endif
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/* Additional PCI configuration registers */
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#define O2_MUX_CONTROL 0x90 /* 32 bit */
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#define O2_MUX_RING_OUT 0x0000000f
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#define O2_MUX_SKTB_ACTV 0x000000f0
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#define O2_MUX_SCTA_ACTV_ENA 0x00000100
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#define O2_MUX_SCTB_ACTV_ENA 0x00000200
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#define O2_MUX_SER_IRQ_ROUTE 0x0000e000
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#define O2_MUX_SER_PCI 0x00010000
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#define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
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#define O2_MUX_SKTB_TURBO 0x00300000
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#define O2_MUX_AUX_VCC_3V 0x00400000
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#define O2_MUX_PCI_VCC_5V 0x00800000
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#define O2_MUX_PME_MUX 0x0f000000
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/* Additional ExCA registers */
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#define O2_MODE_A 0x38
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#define O2_MODE_A_2 0x26 /* for 6833B, 6860C */
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#define O2_MODE_A_CD_PULSE 0x04
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#define O2_MODE_A_SUSP_EDGE 0x08
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#define O2_MODE_A_HOST_SUSP 0x10
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#define O2_MODE_A_PWR_MASK 0x60
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#define O2_MODE_A_QUIET 0x80
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#define O2_MODE_B 0x39
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#define O2_MODE_B_2 0x2e /* for 6833B, 6860C */
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#define O2_MODE_B_IDENT 0x03
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#define O2_MODE_B_ID_BSTEP 0x00
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#define O2_MODE_B_ID_CSTEP 0x01
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#define O2_MODE_B_ID_O2 0x02
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#define O2_MODE_B_VS1 0x04
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#define O2_MODE_B_VS2 0x08
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#define O2_MODE_B_IRQ15_RI 0x80
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#define O2_MODE_C 0x3a
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#define O2_MODE_C_DREQ_MASK 0x03
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#define O2_MODE_C_DREQ_INPACK 0x01
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#define O2_MODE_C_DREQ_WP 0x02
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#define O2_MODE_C_DREQ_BVD2 0x03
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#define O2_MODE_C_ZVIDEO 0x08
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#define O2_MODE_C_IREQ_SEL 0x30
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#define O2_MODE_C_MGMT_SEL 0xc0
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#define O2_MODE_D 0x3b
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#define O2_MODE_D_IRQ_MODE 0x03
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#define O2_MODE_D_PCI_CLKRUN 0x04
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#define O2_MODE_D_CB_CLKRUN 0x08
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#define O2_MODE_D_SKT_ACTV 0x20
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#define O2_MODE_D_PCI_FIFO 0x40 /* for OZ6729, OZ6730 */
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#define O2_MODE_D_W97_IRQ 0x40
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#define O2_MODE_D_ISA_IRQ 0x80
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#define O2_MHPG_DMA 0x3c
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#define O2_MHPG_CHANNEL 0x07
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#define O2_MHPG_CINT_ENA 0x08
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#define O2_MHPG_CSC_ENA 0x10
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#define O2_FIFO_ENA 0x3d
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#define O2_FIFO_ZVIDEO_3 0x08
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#define O2_FIFO_PCI_FIFO 0x10
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#define O2_FIFO_POSTWR 0x40
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#define O2_FIFO_BUFFER 0x80
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#define O2_MODE_E 0x3e
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#define O2_MODE_E_MHPG_DMA 0x01
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#define O2_MODE_E_SPKR_OUT 0x02
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#define O2_MODE_E_LED_OUT 0x08
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#define O2_MODE_E_SKTA_ACTV 0x10
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#define O2_RESERVED1 0x94
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#define O2_RESERVED2 0xD4
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#define O2_RES_READ_PREFETCH 0x02
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#define O2_RES_WRITE_BURST 0x08
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static int o2micro_override(struct yenta_socket *socket)
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{
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/*
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* 'reserved' register at 0x94/D4. allows setting read prefetch and write
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* bursting. read prefetching for example makes the RME Hammerfall DSP
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* working. for some bridges it is at 0x94, for others at 0xD4. it's
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* ok to write to both registers on all O2 bridges.
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* from Eric Still, 02Micro.
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*/
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u8 a, b;
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if (PCI_FUNC(socket->dev->devfn) == 0) {
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a = config_readb(socket, O2_RESERVED1);
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b = config_readb(socket, O2_RESERVED2);
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dev_printk(KERN_INFO, &socket->dev->dev,
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"O2: res at 0x94/0xD4: %02x/%02x\n", a, b);
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switch (socket->dev->device) {
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/*
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* older bridges have problems with both read prefetch and write
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* bursting depending on the combination of the chipset, bridge
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* and the cardbus card. so disable them to be on the safe side.
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*/
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case PCI_DEVICE_ID_O2_6729:
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case PCI_DEVICE_ID_O2_6730:
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case PCI_DEVICE_ID_O2_6812:
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case PCI_DEVICE_ID_O2_6832:
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case PCI_DEVICE_ID_O2_6836:
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dev_printk(KERN_INFO, &socket->dev->dev,
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"Yenta O2: old bridge, disabling read "
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"prefetch/write burst\n");
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config_writeb(socket, O2_RESERVED1,
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a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
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config_writeb(socket, O2_RESERVED2,
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b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
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break;
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default:
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dev_printk(KERN_INFO , &socket->dev->dev,
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"O2: enabling read prefetch/write burst\n");
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config_writeb(socket, O2_RESERVED1,
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a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
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config_writeb(socket, O2_RESERVED2,
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b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
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}
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}
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return 0;
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}
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static void o2micro_restore_state(struct yenta_socket *socket)
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{
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/*
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* as long as read prefetch is the only thing in
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* o2micro_override, it's safe to call it from here
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*/
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o2micro_override(socket);
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}
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#endif /* _LINUX_O2MICRO_H */
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