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8c3ad488fe
Dummy buffer is used for half duplex transfers that don't have TX or RX buffer set. Instead of own dummy buffer management here let the SPI core to handle it by setting the SPI_MASTER_MUST_RX and SPI_MASTER_MUST_TX flags. Then core makes sure both transfer buffers are set. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
162 lines
4.0 KiB
C
162 lines
4.0 KiB
C
/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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* Copyright (C) 2013, Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef SPI_PXA2XX_H
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#define SPI_PXA2XX_H
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#include <linux/atomic.h>
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#include <linux/dmaengine.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/scatterlist.h>
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#include <linux/sizes.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/pxa2xx_spi.h>
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struct driver_data {
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/* Driver model hookup */
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struct platform_device *pdev;
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/* SSP Info */
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struct ssp_device *ssp;
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/* SPI framework hookup */
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enum pxa_ssp_type ssp_type;
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struct spi_master *master;
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/* PXA hookup */
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struct pxa2xx_spi_master *master_info;
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/* SSP register addresses */
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void __iomem *ioaddr;
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u32 ssdr_physical;
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/* SSP masks*/
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u32 dma_cr1;
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u32 int_cr1;
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u32 clear_sr;
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u32 mask_sr;
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/* Message Transfer pump */
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struct tasklet_struct pump_transfers;
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/* DMA engine support */
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struct dma_chan *rx_chan;
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struct dma_chan *tx_chan;
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struct sg_table rx_sgt;
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struct sg_table tx_sgt;
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int rx_nents;
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int tx_nents;
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atomic_t dma_running;
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/* Current message transfer state info */
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struct spi_message *cur_msg;
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struct spi_transfer *cur_transfer;
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struct chip_data *cur_chip;
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size_t len;
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void *tx;
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void *tx_end;
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void *rx;
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void *rx_end;
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int dma_mapped;
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u8 n_bytes;
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int (*write)(struct driver_data *drv_data);
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int (*read)(struct driver_data *drv_data);
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irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
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void (*cs_control)(u32 command);
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void __iomem *lpss_base;
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};
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struct chip_data {
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u32 cr1;
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u32 dds_rate;
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u32 timeout;
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u8 n_bytes;
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u32 dma_burst_size;
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u32 threshold;
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u32 dma_threshold;
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u16 lpss_rx_threshold;
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u16 lpss_tx_threshold;
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u8 enable_dma;
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union {
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int gpio_cs;
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unsigned int frm;
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};
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int gpio_cs_inverted;
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int (*write)(struct driver_data *drv_data);
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int (*read)(struct driver_data *drv_data);
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void (*cs_control)(u32 command);
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};
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static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
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unsigned reg)
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{
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return __raw_readl(drv_data->ioaddr + reg);
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}
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static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
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unsigned reg, u32 val)
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{
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__raw_writel(val, drv_data->ioaddr + reg);
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}
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#define START_STATE ((void *)0)
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#define RUNNING_STATE ((void *)1)
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#define DONE_STATE ((void *)2)
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#define ERROR_STATE ((void *)-1)
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#define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
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#define DMA_ALIGNMENT 8
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static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
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{
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switch (drv_data->ssp_type) {
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case PXA25x_SSP:
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case CE4100_SSP:
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case QUARK_X1000_SSP:
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return 1;
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default:
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return 0;
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}
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}
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static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
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{
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if (drv_data->ssp_type == CE4100_SSP ||
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drv_data->ssp_type == QUARK_X1000_SSP)
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val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
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pxa2xx_spi_write(drv_data, SSSR, val);
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}
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extern int pxa2xx_spi_flush(struct driver_data *drv_data);
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extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
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#define MAX_DMA_LEN SZ_64K
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#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
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extern bool pxa2xx_spi_dma_is_possible(size_t len);
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extern int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data);
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extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
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extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
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extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
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extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
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extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
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extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
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struct spi_device *spi,
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u8 bits_per_word,
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u32 *burst_code,
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u32 *threshold);
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#endif /* SPI_PXA2XX_H */
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