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0896d4d4fb
To properly support sysrq on uartDM hardware we need to properly handle break characters. With the DM hardware the fifo can pack 4 characters at a time, where a break is indicated by an all zero byte. Unfortunately, we can't differentiate between an all zero byte for a break and an all zero byte of data, so try and do as best we can. First unmask the RX break start interrupt and record the interrupt when it arrives. Then while processing the fifo, detect the break by searching for an all zero character as long as we recently received an RX break start interrupt. This should make sysrq work fairly well. Cc: Frank Rowand <frank.rowand@sonymobile.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
185 lines
5.4 KiB
C
185 lines
5.4 KiB
C
/*
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* Copyright (C) 2007 Google, Inc.
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* Author: Robert Love <rlove@google.com>
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
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#define __DRIVERS_SERIAL_MSM_SERIAL_H
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#define UART_MR1 0x0000
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#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
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#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
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#define UART_MR1_RX_RDY_CTL (1 << 7)
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#define UART_MR1_CTS_CTL (1 << 6)
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#define UART_MR2 0x0004
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#define UART_MR2_ERROR_MODE (1 << 6)
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#define UART_MR2_BITS_PER_CHAR 0x30
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#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
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#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
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#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
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#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
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#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
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#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
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#define UART_MR2_PARITY_MODE_NONE 0x0
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#define UART_MR2_PARITY_MODE_ODD 0x1
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#define UART_MR2_PARITY_MODE_EVEN 0x2
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#define UART_MR2_PARITY_MODE_SPACE 0x3
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#define UART_MR2_PARITY_MODE 0x3
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#define UART_CSR 0x0008
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#define UART_TF 0x000C
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#define UARTDM_TF 0x0070
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#define UART_CR 0x0010
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#define UART_CR_CMD_NULL (0 << 4)
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#define UART_CR_CMD_RESET_RX (1 << 4)
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#define UART_CR_CMD_RESET_TX (2 << 4)
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#define UART_CR_CMD_RESET_ERR (3 << 4)
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#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
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#define UART_CR_CMD_START_BREAK (5 << 4)
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#define UART_CR_CMD_STOP_BREAK (6 << 4)
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#define UART_CR_CMD_RESET_CTS (7 << 4)
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#define UART_CR_CMD_RESET_STALE_INT (8 << 4)
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#define UART_CR_CMD_PACKET_MODE (9 << 4)
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#define UART_CR_CMD_MODE_RESET (12 << 4)
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#define UART_CR_CMD_SET_RFR (13 << 4)
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#define UART_CR_CMD_RESET_RFR (14 << 4)
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#define UART_CR_CMD_PROTECTION_EN (16 << 4)
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#define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
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#define UART_CR_CMD_FORCE_STALE (4 << 8)
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#define UART_CR_CMD_RESET_TX_READY (3 << 8)
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#define UART_CR_TX_DISABLE (1 << 3)
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#define UART_CR_TX_ENABLE (1 << 2)
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#define UART_CR_RX_DISABLE (1 << 1)
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#define UART_CR_RX_ENABLE (1 << 0)
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#define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
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#define UART_IMR 0x0014
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#define UART_IMR_TXLEV (1 << 0)
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#define UART_IMR_RXSTALE (1 << 3)
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#define UART_IMR_RXLEV (1 << 4)
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#define UART_IMR_DELTA_CTS (1 << 5)
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#define UART_IMR_CURRENT_CTS (1 << 6)
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#define UART_IMR_RXBREAK_START (1 << 10)
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#define UART_IPR_RXSTALE_LAST 0x20
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#define UART_IPR_STALE_LSB 0x1F
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#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
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#define UART_IPR 0x0018
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#define UART_TFWR 0x001C
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#define UART_RFWR 0x0020
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#define UART_HCR 0x0024
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#define UART_MREG 0x0028
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#define UART_NREG 0x002C
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#define UART_DREG 0x0030
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#define UART_MNDREG 0x0034
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#define UART_IRDA 0x0038
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#define UART_MISR_MODE 0x0040
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#define UART_MISR_RESET 0x0044
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#define UART_MISR_EXPORT 0x0048
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#define UART_MISR_VAL 0x004C
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#define UART_TEST_CTRL 0x0050
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#define UART_SR 0x0008
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#define UART_SR_HUNT_CHAR (1 << 7)
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#define UART_SR_RX_BREAK (1 << 6)
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#define UART_SR_PAR_FRAME_ERR (1 << 5)
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#define UART_SR_OVERRUN (1 << 4)
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#define UART_SR_TX_EMPTY (1 << 3)
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#define UART_SR_TX_READY (1 << 2)
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#define UART_SR_RX_FULL (1 << 1)
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#define UART_SR_RX_READY (1 << 0)
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#define UART_RF 0x000C
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#define UARTDM_RF 0x0070
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#define UART_MISR 0x0010
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#define UART_ISR 0x0014
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#define UART_ISR_TX_READY (1 << 7)
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#define UARTDM_RXFS 0x50
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#define UARTDM_RXFS_BUF_SHIFT 0x7
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#define UARTDM_RXFS_BUF_MASK 0x7
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#define UARTDM_DMEN 0x3C
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#define UARTDM_DMEN_RX_SC_ENABLE BIT(5)
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#define UARTDM_DMEN_TX_SC_ENABLE BIT(4)
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#define UARTDM_DMRX 0x34
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#define UARTDM_NCF_TX 0x40
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#define UARTDM_RX_TOTAL_SNAP 0x38
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#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
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static inline
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void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
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{
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writel_relaxed(val, port->membase + off);
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}
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static inline
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unsigned int msm_read(struct uart_port *port, unsigned int off)
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{
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return readl_relaxed(port->membase + off);
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}
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/*
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* Setup the MND registers to use the TCXO clock.
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*/
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static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
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{
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msm_write(port, 0x06, UART_MREG);
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msm_write(port, 0xF1, UART_NREG);
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msm_write(port, 0x0F, UART_DREG);
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msm_write(port, 0x1A, UART_MNDREG);
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port->uartclk = 1843200;
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}
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/*
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* Setup the MND registers to use the TCXO clock divided by 4.
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*/
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static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
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{
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msm_write(port, 0x18, UART_MREG);
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msm_write(port, 0xF6, UART_NREG);
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msm_write(port, 0x0F, UART_DREG);
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msm_write(port, 0x0A, UART_MNDREG);
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port->uartclk = 1843200;
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}
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static inline
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void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
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{
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if (port->uartclk == 19200000)
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msm_serial_set_mnd_regs_tcxo(port);
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else if (port->uartclk == 4800000)
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msm_serial_set_mnd_regs_tcxoby4(port);
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}
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/*
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* TROUT has a specific defect that makes it report it's uartclk
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* as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
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* cases TROUT to use the right clock.
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*/
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#ifdef CONFIG_MACH_TROUT
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#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
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#else
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#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
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#endif
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#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */
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