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783944feaa
Use a matching device tree node to initialize the flow controller driver instead of hard-coding the I/O address. This is necessary to get rid of the iomap.h include, which in turn make it easier to share this code with 64-bit Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/*
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* arch/arm/mach-tegra/flowctrl.h
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*
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* functions and macros to control the flowcontroller
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*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MACH_TEGRA_FLOWCTRL_H
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#define __MACH_TEGRA_FLOWCTRL_H
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#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTRL_WAITEVENT (2 << 29)
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#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
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#define FLOW_CTRL_JTAG_RESUME (1 << 28)
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#define FLOW_CTRL_SCLK_RESUME (1 << 27)
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#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
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#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
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#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
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#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
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#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
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#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
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#define FLOW_CTRL_CPU0_CSR 0x8
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#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
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#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
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#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
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#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
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#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
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FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
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FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
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#define FLOW_CTRL_CSR_ENABLE (1 << 0)
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#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTRL_CPU1_CSR 0x18
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#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
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#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
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#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
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#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
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#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
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#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
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#ifndef __ASSEMBLY__
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u32 flowctrl_read_cpu_csr(unsigned int cpuid);
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void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
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void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
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void flowctrl_cpu_suspend_enter(unsigned int cpuid);
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void flowctrl_cpu_suspend_exit(unsigned int cpuid);
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void tegra_flowctrl_init(void);
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#endif
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#endif
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