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751f7e999a
Add cpuidle support for i.MX6SL, currently only support
two cpuidle levels(ARM wfi and WAIT mode), and add software
workaround for WAIT mode errata as below:
ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
during WAIT mode entry process could cause cache memory
corruption.
Software workaround:
To prevent this issue from occurring, software should ensure that
the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
entering WAIT mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
31 lines
696 B
C
31 lines
696 B
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2012 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifdef CONFIG_CPU_IDLE
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extern int imx5_cpuidle_init(void);
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extern int imx6q_cpuidle_init(void);
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extern int imx6sl_cpuidle_init(void);
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#else
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static inline int imx5_cpuidle_init(void)
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{
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return 0;
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}
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static inline int imx6q_cpuidle_init(void)
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{
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return 0;
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}
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static inline int imx6sl_cpuidle_init(void)
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{
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return 0;
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}
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#endif
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