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6b22194d5e
Add binding documentation for the nvidia,tegra124-emc device tree node. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
375 lines
11 KiB
Plaintext
375 lines
11 KiB
Plaintext
NVIDIA Tegra124 SoC EMC (external memory controller)
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====================================================
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Required properties :
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- compatible : Should be "nvidia,tegra124-emc".
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- reg : physical base address and length of the controller's registers.
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- nvidia,memory-controller : phandle of the MC driver.
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The node should contain a "emc-timings" subnode for each supported RAM type
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(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
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being its RAM_CODE.
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Required properties for "emc-timings" nodes :
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- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
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used for.
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Each "emc-timings" node should contain a "timing" subnode for every supported
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EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
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their unit address.
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Required properties for "timing" nodes :
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- clock-frequency : Should contain the memory clock rate in Hz.
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- The following properties contain EMC timing characterization values
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(specified in the board documentation) :
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- nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
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- nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
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- nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
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- nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
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- nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
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- nvidia,emc-cfg : EMC_CFG
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- nvidia,emc-cfg-2 : EMC_CFG_2
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- nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
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- nvidia,emc-mode-1 : Mode Register 1
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- nvidia,emc-mode-2 : Mode Register 2
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- nvidia,emc-mode-4 : Mode Register 4
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- nvidia,emc-mode-reset : Mode Register 0
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- nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
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- nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
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- nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
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- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
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- nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
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- nvidia,emc-configuration : EMC timing characterization data. These are the
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registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
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be specified, according to the board documentation:
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EMC_RC
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EMC_RFC
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EMC_RFC_SLR
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EMC_RAS
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EMC_RP
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EMC_R2W
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EMC_W2R
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EMC_R2P
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EMC_W2P
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EMC_RD_RCD
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EMC_WR_RCD
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EMC_RRD
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EMC_REXT
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EMC_WEXT
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EMC_WDV
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EMC_WDV_MASK
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EMC_QUSE
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EMC_QUSE_WIDTH
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EMC_IBDLY
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EMC_EINPUT
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EMC_EINPUT_DURATION
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EMC_PUTERM_EXTRA
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EMC_PUTERM_WIDTH
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EMC_PUTERM_ADJ
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EMC_CDB_CNTL_1
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EMC_CDB_CNTL_2
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EMC_CDB_CNTL_3
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EMC_QRST
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EMC_QSAFE
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EMC_RDV
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EMC_RDV_MASK
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EMC_REFRESH
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EMC_BURST_REFRESH_NUM
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EMC_PRE_REFRESH_REQ_CNT
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EMC_PDEX2WR
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EMC_PDEX2RD
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EMC_PCHG2PDEN
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EMC_ACT2PDEN
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EMC_AR2PDEN
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EMC_RW2PDEN
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EMC_TXSR
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EMC_TXSRDLL
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EMC_TCKE
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EMC_TCKESR
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EMC_TPD
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EMC_TFAW
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EMC_TRPAB
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EMC_TCLKSTABLE
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EMC_TCLKSTOP
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EMC_TREFBW
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EMC_FBIO_CFG6
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EMC_ODT_WRITE
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EMC_ODT_READ
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EMC_FBIO_CFG5
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EMC_CFG_DIG_DLL
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EMC_CFG_DIG_DLL_PERIOD
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EMC_DLL_XFORM_DQS0
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EMC_DLL_XFORM_DQS1
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EMC_DLL_XFORM_DQS2
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EMC_DLL_XFORM_DQS3
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EMC_DLL_XFORM_DQS4
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EMC_DLL_XFORM_DQS5
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EMC_DLL_XFORM_DQS6
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EMC_DLL_XFORM_DQS7
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EMC_DLL_XFORM_DQS8
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EMC_DLL_XFORM_DQS9
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EMC_DLL_XFORM_DQS10
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EMC_DLL_XFORM_DQS11
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EMC_DLL_XFORM_DQS12
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EMC_DLL_XFORM_DQS13
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EMC_DLL_XFORM_DQS14
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EMC_DLL_XFORM_DQS15
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EMC_DLL_XFORM_QUSE0
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EMC_DLL_XFORM_QUSE1
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EMC_DLL_XFORM_QUSE2
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EMC_DLL_XFORM_QUSE3
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EMC_DLL_XFORM_QUSE4
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EMC_DLL_XFORM_QUSE5
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EMC_DLL_XFORM_QUSE6
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EMC_DLL_XFORM_QUSE7
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EMC_DLL_XFORM_ADDR0
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EMC_DLL_XFORM_ADDR1
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EMC_DLL_XFORM_ADDR2
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EMC_DLL_XFORM_ADDR3
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EMC_DLL_XFORM_ADDR4
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EMC_DLL_XFORM_ADDR5
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EMC_DLL_XFORM_QUSE8
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EMC_DLL_XFORM_QUSE9
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EMC_DLL_XFORM_QUSE10
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EMC_DLL_XFORM_QUSE11
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EMC_DLL_XFORM_QUSE12
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EMC_DLL_XFORM_QUSE13
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EMC_DLL_XFORM_QUSE14
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EMC_DLL_XFORM_QUSE15
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EMC_DLI_TRIM_TXDQS0
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EMC_DLI_TRIM_TXDQS1
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EMC_DLI_TRIM_TXDQS2
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EMC_DLI_TRIM_TXDQS3
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EMC_DLI_TRIM_TXDQS4
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EMC_DLI_TRIM_TXDQS5
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EMC_DLI_TRIM_TXDQS6
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EMC_DLI_TRIM_TXDQS7
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EMC_DLI_TRIM_TXDQS8
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EMC_DLI_TRIM_TXDQS9
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EMC_DLI_TRIM_TXDQS10
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EMC_DLI_TRIM_TXDQS11
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EMC_DLI_TRIM_TXDQS12
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EMC_DLI_TRIM_TXDQS13
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EMC_DLI_TRIM_TXDQS14
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EMC_DLI_TRIM_TXDQS15
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EMC_DLL_XFORM_DQ0
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EMC_DLL_XFORM_DQ1
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EMC_DLL_XFORM_DQ2
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EMC_DLL_XFORM_DQ3
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EMC_DLL_XFORM_DQ4
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EMC_DLL_XFORM_DQ5
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EMC_DLL_XFORM_DQ6
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EMC_DLL_XFORM_DQ7
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EMC_XM2CMDPADCTRL
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EMC_XM2CMDPADCTRL4
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EMC_XM2CMDPADCTRL5
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EMC_XM2DQPADCTRL2
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EMC_XM2DQPADCTRL3
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EMC_XM2CLKPADCTRL
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EMC_XM2CLKPADCTRL2
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EMC_XM2COMPPADCTRL
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EMC_XM2VTTGENPADCTRL
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EMC_XM2VTTGENPADCTRL2
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EMC_XM2VTTGENPADCTRL3
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EMC_XM2DQSPADCTRL3
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EMC_XM2DQSPADCTRL4
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EMC_XM2DQSPADCTRL5
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EMC_XM2DQSPADCTRL6
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EMC_DSR_VTTGEN_DRV
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EMC_TXDSRVTTGEN
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EMC_FBIO_SPARE
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EMC_ZCAL_WAIT_CNT
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EMC_MRS_WAIT_CNT2
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EMC_CTT
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EMC_CTT_DURATION
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EMC_CFG_PIPE
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EMC_DYN_SELF_REF_CONTROL
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EMC_QPOP
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Example SoC include file:
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/ {
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emc@0,7001b000 {
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compatible = "nvidia,tegra124-emc";
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reg = <0x0 0x7001b000 0x0 0x1000>;
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nvidia,memory-controller = <&mc>;
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};
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};
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Example board file:
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/ {
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emc@0,7001b000 {
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,emc-zcal-cnt-long = <0x00000042>;
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nvidia,emc-auto-cal-interval = <0x001fffff>;
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nvidia,emc-ctt-term-ctrl = <0x00000802>;
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nvidia,emc-cfg = <0x73240000>;
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nvidia,emc-cfg-2 = <0x000008c5>;
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nvidia,emc-sel-dpd-ctrl = <0x00040128>;
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nvidia,emc-bgbias-ctl0 = <0x00000008>;
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nvidia,emc-auto-cal-config = <0xa1430000>;
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nvidia,emc-auto-cal-config2 = <0x00000000>;
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nvidia,emc-auto-cal-config3 = <0x00000000>;
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nvidia,emc-mode-reset = <0x80001221>;
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nvidia,emc-mode-1 = <0x80100003>;
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nvidia,emc-mode-2 = <0x80200008>;
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nvidia,emc-mode-4 = <0x00000000>;
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nvidia,emc-configuration = <
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0x00000000 /* EMC_RC */
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0x00000003 /* EMC_RFC */
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0x00000000 /* EMC_RFC_SLR */
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0x00000000 /* EMC_RAS */
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0x00000000 /* EMC_RP */
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0x00000004 /* EMC_R2W */
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0x0000000a /* EMC_W2R */
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0x00000003 /* EMC_R2P */
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0x0000000b /* EMC_W2P */
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0x00000000 /* EMC_RD_RCD */
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0x00000000 /* EMC_WR_RCD */
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0x00000003 /* EMC_RRD */
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0x00000003 /* EMC_REXT */
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0x00000000 /* EMC_WEXT */
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0x00000006 /* EMC_WDV */
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0x00000006 /* EMC_WDV_MASK */
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0x00000006 /* EMC_QUSE */
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0x00000002 /* EMC_QUSE_WIDTH */
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0x00000000 /* EMC_IBDLY */
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0x00000005 /* EMC_EINPUT */
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0x00000005 /* EMC_EINPUT_DURATION */
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0x00010000 /* EMC_PUTERM_EXTRA */
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0x00000003 /* EMC_PUTERM_WIDTH */
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0x00000000 /* EMC_PUTERM_ADJ */
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0x00000000 /* EMC_CDB_CNTL_1 */
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0x00000000 /* EMC_CDB_CNTL_2 */
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0x00000000 /* EMC_CDB_CNTL_3 */
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0x00000004 /* EMC_QRST */
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0x0000000c /* EMC_QSAFE */
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0x0000000d /* EMC_RDV */
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0x0000000f /* EMC_RDV_MASK */
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0x00000060 /* EMC_REFRESH */
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0x00000000 /* EMC_BURST_REFRESH_NUM */
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0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
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0x00000002 /* EMC_PDEX2WR */
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0x00000002 /* EMC_PDEX2RD */
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0x00000001 /* EMC_PCHG2PDEN */
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0x00000000 /* EMC_ACT2PDEN */
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0x00000007 /* EMC_AR2PDEN */
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0x0000000f /* EMC_RW2PDEN */
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0x00000005 /* EMC_TXSR */
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0x00000005 /* EMC_TXSRDLL */
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0x00000004 /* EMC_TCKE */
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0x00000005 /* EMC_TCKESR */
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0x00000004 /* EMC_TPD */
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0x00000000 /* EMC_TFAW */
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0x00000000 /* EMC_TRPAB */
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0x00000005 /* EMC_TCLKSTABLE */
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0x00000005 /* EMC_TCLKSTOP */
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0x00000064 /* EMC_TREFBW */
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0x00000000 /* EMC_FBIO_CFG6 */
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0x00000000 /* EMC_ODT_WRITE */
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0x00000000 /* EMC_ODT_READ */
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0x106aa298 /* EMC_FBIO_CFG5 */
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0x002c00a0 /* EMC_CFG_DIG_DLL */
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0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
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0x00064000 /* EMC_DLL_XFORM_DQS0 */
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0x00064000 /* EMC_DLL_XFORM_DQS1 */
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0x00064000 /* EMC_DLL_XFORM_DQS2 */
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0x00064000 /* EMC_DLL_XFORM_DQS3 */
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0x00064000 /* EMC_DLL_XFORM_DQS4 */
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0x00064000 /* EMC_DLL_XFORM_DQS5 */
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0x00064000 /* EMC_DLL_XFORM_DQS6 */
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0x00064000 /* EMC_DLL_XFORM_DQS7 */
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0x00064000 /* EMC_DLL_XFORM_DQS8 */
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0x00064000 /* EMC_DLL_XFORM_DQS9 */
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0x00064000 /* EMC_DLL_XFORM_DQS10 */
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0x00064000 /* EMC_DLL_XFORM_DQS11 */
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0x00064000 /* EMC_DLL_XFORM_DQS12 */
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0x00064000 /* EMC_DLL_XFORM_DQS13 */
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0x00064000 /* EMC_DLL_XFORM_DQS14 */
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0x00064000 /* EMC_DLL_XFORM_DQS15 */
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0x00000000 /* EMC_DLL_XFORM_QUSE0 */
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0x00000000 /* EMC_DLL_XFORM_QUSE1 */
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0x00000000 /* EMC_DLL_XFORM_QUSE2 */
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0x00000000 /* EMC_DLL_XFORM_QUSE3 */
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0x00000000 /* EMC_DLL_XFORM_QUSE4 */
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0x00000000 /* EMC_DLL_XFORM_QUSE5 */
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0x00000000 /* EMC_DLL_XFORM_QUSE6 */
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0x00000000 /* EMC_DLL_XFORM_QUSE7 */
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0x00000000 /* EMC_DLL_XFORM_ADDR0 */
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0x00000000 /* EMC_DLL_XFORM_ADDR1 */
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0x00000000 /* EMC_DLL_XFORM_ADDR2 */
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0x00000000 /* EMC_DLL_XFORM_ADDR3 */
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0x00000000 /* EMC_DLL_XFORM_ADDR4 */
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0x00000000 /* EMC_DLL_XFORM_ADDR5 */
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0x00000000 /* EMC_DLL_XFORM_QUSE8 */
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0x00000000 /* EMC_DLL_XFORM_QUSE9 */
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0x00000000 /* EMC_DLL_XFORM_QUSE10 */
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0x00000000 /* EMC_DLL_XFORM_QUSE11 */
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0x00000000 /* EMC_DLL_XFORM_QUSE12 */
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0x00000000 /* EMC_DLL_XFORM_QUSE13 */
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0x00000000 /* EMC_DLL_XFORM_QUSE14 */
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0x00000000 /* EMC_DLL_XFORM_QUSE15 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
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0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
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0x000fc000 /* EMC_DLL_XFORM_DQ0 */
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0x000fc000 /* EMC_DLL_XFORM_DQ1 */
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0x000fc000 /* EMC_DLL_XFORM_DQ2 */
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0x000fc000 /* EMC_DLL_XFORM_DQ3 */
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0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
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0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
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0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
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0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
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0x10000280 /* EMC_XM2CMDPADCTRL */
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0x00000000 /* EMC_XM2CMDPADCTRL4 */
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0x00111111 /* EMC_XM2CMDPADCTRL5 */
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0x00000000 /* EMC_XM2DQPADCTRL2 */
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0x00000000 /* EMC_XM2DQPADCTRL3 */
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0x77ffc081 /* EMC_XM2CLKPADCTRL */
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0x00000e0e /* EMC_XM2CLKPADCTRL2 */
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0x81f1f108 /* EMC_XM2COMPPADCTRL */
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0x07070004 /* EMC_XM2VTTGENPADCTRL */
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0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
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0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
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0x51451400 /* EMC_XM2DQSPADCTRL3 */
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0x00514514 /* EMC_XM2DQSPADCTRL4 */
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0x00514514 /* EMC_XM2DQSPADCTRL5 */
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0x51451400 /* EMC_XM2DQSPADCTRL6 */
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0x0000003f /* EMC_DSR_VTTGEN_DRV */
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0x00000007 /* EMC_TXDSRVTTGEN */
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0x00000000 /* EMC_FBIO_SPARE */
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0x00000042 /* EMC_ZCAL_WAIT_CNT */
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0x000e000e /* EMC_MRS_WAIT_CNT2 */
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0x00000000 /* EMC_CTT */
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0x00000003 /* EMC_CTT_DURATION */
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0x0000f2f3 /* EMC_CFG_PIPE */
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0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
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0x0000000a /* EMC_QPOP */
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>;
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};
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};
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};
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};
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