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8d4d9f5208
This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: Mike Turquette <mturquette@linaro.org>
18 lines
753 B
Plaintext
18 lines
753 B
Plaintext
Device Tree Clock bindings for Calxeda highbank platform
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"calxeda,hb-pll-clock" - for a PLL clock
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"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
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A9 clock.
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"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
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"calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
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- reg : shall be the control register offset from SYSREGs base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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- #clock-cells : from common clock binding; shall be set to 0.
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