mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-16 17:23:55 +08:00
1abd350237
Robert Jarzmik reports that his PXA25x system fails to boot with 4.12, failing at __flush_whole_cache in arch/arm/mm/proc-xscale.S:215: 0xc0019e20 <+0>: ldr r1, [pc, #788] 0xc0019e24 <+4>: ldr r0, [r1] <== here with r1 containing 0xc06f82cd, which is the address of "clean_addr". Examination of the System.map shows: c06f22c8 D user_pmd_table c06f22cc d __warned.19178 c06f22cd d clean_addr indicating that a .data.unlikely section has appeared just before the .data section from proc-xscale.S. According to objdump -h, it appears that our assembly files default their .data alignment to 2**0, which is bad news if the preceding .data section size is not power-of-2 aligned at link time. Add the appropriate .align directives to all assembly files in arch/arm that are missing them where we require an appropriate alignment. Reported-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
74 lines
1.8 KiB
ArmAsm
74 lines
1.8 KiB
ArmAsm
/*
|
|
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
|
|
* Author: Tony Xie <tony.xie@rock-chips.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
*/
|
|
|
|
#include <linux/linkage.h>
|
|
#include <asm/assembler.h>
|
|
#include <asm/memory.h>
|
|
|
|
.data
|
|
/*
|
|
* this code will be copied from
|
|
* ddr to sram for system resumeing.
|
|
* so it is ".data section".
|
|
*/
|
|
.align 2
|
|
|
|
ENTRY(rockchip_slp_cpu_resume)
|
|
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
|
|
mrc p15, 0, r1, c0, c0, 5
|
|
and r1, r1, #0xf
|
|
cmp r1, #0
|
|
/* olny cpu0 can continue to run, the others is halt here */
|
|
beq cpu0run
|
|
secondary_loop:
|
|
wfe
|
|
b secondary_loop
|
|
cpu0run:
|
|
ldr r3, rkpm_bootdata_l2ctlr_f
|
|
cmp r3, #0
|
|
beq sp_set
|
|
ldr r3, rkpm_bootdata_l2ctlr
|
|
mcr p15, 1, r3, c9, c0, 2
|
|
sp_set:
|
|
ldr sp, rkpm_bootdata_cpusp
|
|
ldr r1, rkpm_bootdata_cpu_code
|
|
bx r1
|
|
ENDPROC(rockchip_slp_cpu_resume)
|
|
|
|
/* Parameters filled in by the kernel */
|
|
|
|
/* Flag for whether to restore L2CTLR on resume */
|
|
.global rkpm_bootdata_l2ctlr_f
|
|
rkpm_bootdata_l2ctlr_f:
|
|
.long 0
|
|
|
|
/* Saved L2CTLR to restore on resume */
|
|
.global rkpm_bootdata_l2ctlr
|
|
rkpm_bootdata_l2ctlr:
|
|
.long 0
|
|
|
|
/* CPU resume SP addr */
|
|
.globl rkpm_bootdata_cpusp
|
|
rkpm_bootdata_cpusp:
|
|
.long 0
|
|
|
|
/* CPU resume function (physical address) */
|
|
.globl rkpm_bootdata_cpu_code
|
|
rkpm_bootdata_cpu_code:
|
|
.long 0
|
|
|
|
ENTRY(rk3288_bootram_sz)
|
|
.word . - rockchip_slp_cpu_resume
|