Andi Kleen d0dc8494cd perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake ... Skylake has a new FRONTEND_LATENCY PEBS event to accurately profile frontend problems (like ITLB or decoding issues). The new event is configured through a separate MSR, which selects a range of sub events. Define the extra MSR as a extra reg and export support for it through sysfs. To avoid duplicating the existing tables use a new function to add new entries to existing tables. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1435707205-6676-4-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>		2015-09-18 09:20:22 +02:00
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asm	perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake	2015-09-18 09:20:22 +02:00
uapi/asm	libnvdimm for 4.3:	2015-09-08 14:35:59 -07:00