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https://github.com/edk2-porting/linux-next.git
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29440a2b4c
- Move cache initialization to C from assembly. - Move anomaly workaround for writing [ID]MEM_CONTROL to assembly, so that we don't have to mess around with .align directives in C source. - Fix a bug where bfin_write_DMEM_CONTROL would write to IMEM_CONTROL - Break out CPLB related code from kernel/setup.c into their own file. - Don't define variables in header files, only declare them. Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/*
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* File: include/asm-blackfin/cplbinit.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#define INITIAL_T 0x1
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#define SWITCH_T 0x2
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#define I_CPLB 0x4
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#define D_CPLB 0x8
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#define IN_KERNEL 1
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enum
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{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
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struct cplb_desc {
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u32 start; /* start address */
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u32 end; /* end address */
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u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
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u16 attr;/* attributes */
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u16 i_conf;/* I-CPLB DATA */
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u16 d_conf;/* D-CPLB DATA */
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u16 valid;/* valid */
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const s8 name[30];/* name */
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};
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struct cplb_tab {
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u_long *tab;
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u16 pos;
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u16 size;
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};
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extern u_long icplb_table[MAX_CPLBS+1];
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extern u_long dcplb_table[MAX_CPLBS+1];
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/* Till here we are discussing about the static memory management model.
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* However, the operating envoronments commonly define more CPLB
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* descriptors to cover the entire addressable memory than will fit into
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* the available on-chip 16 CPLB MMRs. When this happens, the below table
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* will be used which will hold all the potentially required CPLB descriptors
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*
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* This is how Page descriptor Table is implemented in uClinux/Blackfin.
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*/
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#ifdef CONFIG_CPLB_SWITCH_TAB_L1
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extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
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extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
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#ifdef CONFIG_CPLB_INFO
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extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
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extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
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#endif /* CONFIG_CPLB_INFO */
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#else
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extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
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extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
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#ifdef CONFIG_CPLB_INFO
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extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
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extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
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#endif /* CONFIG_CPLB_INFO */
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#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
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extern unsigned long reserved_mem_dcache_on;
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extern unsigned long reserved_mem_icache_on;
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extern void generate_cpl_tables(void);
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