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b6dfb2477f
All watchdog drivers implement the same set of ioctl commands, and fortunately all of them are compatible between 32-bit and 64-bit architectures. Modern drivers always go through drivers/watchdog/wdt.c as an abstraction layer, but older ones implement their own file_operations on a character device for this. Move the handling from fs/compat_ioctl.c into the individual drivers. Note that most of the legacy drivers will never be used on 64-bit hardware, because they are for an old 32-bit SoC implementation, but doing them all at once is safer than trying to guess which ones do or do not need the compat_ioctl handling. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
287 lines
6.0 KiB
C
287 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* sma cpu5 watchdog driver
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*
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* Copyright (C) 2003 Heiko Ronsdorf <hero@ihg.uni-duisburg.de>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/miscdevice.h>
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#include <linux/fs.h>
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#include <linux/ioport.h>
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#include <linux/timer.h>
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#include <linux/completion.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/watchdog.h>
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/* adjustable parameters */
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static int verbose;
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static int port = 0x91;
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static int ticks = 10000;
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static DEFINE_SPINLOCK(cpu5wdt_lock);
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#define PFX "cpu5wdt: "
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#define CPU5WDT_EXTENT 0x0A
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#define CPU5WDT_STATUS_REG 0x00
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#define CPU5WDT_TIME_A_REG 0x02
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#define CPU5WDT_TIME_B_REG 0x03
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#define CPU5WDT_MODE_REG 0x04
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#define CPU5WDT_TRIGGER_REG 0x07
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#define CPU5WDT_ENABLE_REG 0x08
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#define CPU5WDT_RESET_REG 0x09
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#define CPU5WDT_INTERVAL (HZ/10+1)
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/* some device data */
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static struct {
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struct completion stop;
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int running;
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struct timer_list timer;
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int queue;
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int default_ticks;
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unsigned long inuse;
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} cpu5wdt_device;
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/* generic helper functions */
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static void cpu5wdt_trigger(struct timer_list *unused)
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{
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if (verbose > 2)
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pr_debug("trigger at %i ticks\n", ticks);
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if (cpu5wdt_device.running)
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ticks--;
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spin_lock(&cpu5wdt_lock);
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/* keep watchdog alive */
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outb(1, port + CPU5WDT_TRIGGER_REG);
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/* requeue?? */
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if (cpu5wdt_device.queue && ticks)
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mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
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else {
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/* ticks doesn't matter anyway */
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complete(&cpu5wdt_device.stop);
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}
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spin_unlock(&cpu5wdt_lock);
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}
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static void cpu5wdt_reset(void)
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{
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ticks = cpu5wdt_device.default_ticks;
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if (verbose)
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pr_debug("reset (%i ticks)\n", (int) ticks);
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}
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static void cpu5wdt_start(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&cpu5wdt_lock, flags);
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if (!cpu5wdt_device.queue) {
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cpu5wdt_device.queue = 1;
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outb(0, port + CPU5WDT_TIME_A_REG);
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outb(0, port + CPU5WDT_TIME_B_REG);
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outb(1, port + CPU5WDT_MODE_REG);
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outb(0, port + CPU5WDT_RESET_REG);
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outb(0, port + CPU5WDT_ENABLE_REG);
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mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
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}
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/* if process dies, counter is not decremented */
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cpu5wdt_device.running++;
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spin_unlock_irqrestore(&cpu5wdt_lock, flags);
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}
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static int cpu5wdt_stop(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&cpu5wdt_lock, flags);
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if (cpu5wdt_device.running)
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cpu5wdt_device.running = 0;
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ticks = cpu5wdt_device.default_ticks;
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spin_unlock_irqrestore(&cpu5wdt_lock, flags);
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if (verbose)
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pr_crit("stop not possible\n");
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return -EIO;
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}
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/* filesystem operations */
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static int cpu5wdt_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(0, &cpu5wdt_device.inuse))
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return -EBUSY;
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return stream_open(inode, file);
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}
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static int cpu5wdt_release(struct inode *inode, struct file *file)
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{
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clear_bit(0, &cpu5wdt_device.inuse);
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return 0;
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}
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static long cpu5wdt_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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void __user *argp = (void __user *)arg;
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int __user *p = argp;
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unsigned int value;
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static const struct watchdog_info ident = {
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.options = WDIOF_CARDRESET,
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.identity = "CPU5 WDT",
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};
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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if (copy_to_user(argp, &ident, sizeof(ident)))
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return -EFAULT;
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break;
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case WDIOC_GETSTATUS:
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value = inb(port + CPU5WDT_STATUS_REG);
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value = (value >> 2) & 1;
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return put_user(value, p);
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case WDIOC_GETBOOTSTATUS:
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return put_user(0, p);
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case WDIOC_SETOPTIONS:
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if (get_user(value, p))
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return -EFAULT;
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if (value & WDIOS_ENABLECARD)
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cpu5wdt_start();
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if (value & WDIOS_DISABLECARD)
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cpu5wdt_stop();
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break;
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case WDIOC_KEEPALIVE:
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cpu5wdt_reset();
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break;
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default:
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return -ENOTTY;
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}
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return 0;
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}
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static ssize_t cpu5wdt_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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if (!count)
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return -EIO;
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cpu5wdt_reset();
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return count;
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}
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static const struct file_operations cpu5wdt_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.unlocked_ioctl = cpu5wdt_ioctl,
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.compat_ioctl = compat_ptr_ioctl,
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.open = cpu5wdt_open,
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.write = cpu5wdt_write,
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.release = cpu5wdt_release,
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};
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static struct miscdevice cpu5wdt_misc = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &cpu5wdt_fops,
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};
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/* init/exit function */
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static int cpu5wdt_init(void)
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{
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unsigned int val;
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int err;
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if (verbose)
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pr_debug("port=0x%x, verbose=%i\n", port, verbose);
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init_completion(&cpu5wdt_device.stop);
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cpu5wdt_device.queue = 0;
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timer_setup(&cpu5wdt_device.timer, cpu5wdt_trigger, 0);
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cpu5wdt_device.default_ticks = ticks;
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if (!request_region(port, CPU5WDT_EXTENT, PFX)) {
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pr_err("request_region failed\n");
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err = -EBUSY;
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goto no_port;
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}
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/* watchdog reboot? */
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val = inb(port + CPU5WDT_STATUS_REG);
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val = (val >> 2) & 1;
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if (!val)
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pr_info("sorry, was my fault\n");
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err = misc_register(&cpu5wdt_misc);
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if (err < 0) {
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pr_err("misc_register failed\n");
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goto no_misc;
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}
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pr_info("init success\n");
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return 0;
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no_misc:
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release_region(port, CPU5WDT_EXTENT);
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no_port:
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return err;
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}
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static int cpu5wdt_init_module(void)
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{
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return cpu5wdt_init();
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}
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static void cpu5wdt_exit(void)
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{
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if (cpu5wdt_device.queue) {
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cpu5wdt_device.queue = 0;
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wait_for_completion(&cpu5wdt_device.stop);
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del_timer(&cpu5wdt_device.timer);
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}
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misc_deregister(&cpu5wdt_misc);
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release_region(port, CPU5WDT_EXTENT);
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}
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static void cpu5wdt_exit_module(void)
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{
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cpu5wdt_exit();
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}
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/* module entry points */
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module_init(cpu5wdt_init_module);
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module_exit(cpu5wdt_exit_module);
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MODULE_AUTHOR("Heiko Ronsdorf <hero@ihg.uni-duisburg.de>");
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MODULE_DESCRIPTION("sma cpu5 watchdog driver");
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MODULE_SUPPORTED_DEVICE("sma cpu5 watchdog");
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MODULE_LICENSE("GPL");
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module_param_hw(port, int, ioport, 0);
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MODULE_PARM_DESC(port, "base address of watchdog card, default is 0x91");
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module_param(verbose, int, 0);
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MODULE_PARM_DESC(verbose, "be verbose, default is 0 (no)");
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module_param(ticks, int, 0);
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MODULE_PARM_DESC(ticks, "count down ticks, default is 10000");
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