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61790d5bbb
Based on 1 normalized pattern(s): use of this code is subject to the terms and conditions of the gnu general public license version 2 see copying or http www gnu org licenses gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 1 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Armijn Hemel <armijn@tjaldur.nl> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000437.611918838@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
154 lines
3.3 KiB
C
154 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* vSMPowered(tm) systems specific initialization
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* Copyright (C) 2005 ScaleMP Inc.
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*
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* Ravikiran Thirumalai <kiran@scalemp.com>,
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* Shai Fultheim <shai@scalemp.com>
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* Paravirt ops integration: Glauber de Oliveira Costa <gcosta@redhat.com>,
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* Ravikiran Thirumalai <kiran@scalemp.com>
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*/
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#include <linux/init.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/apic.h>
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#include <asm/pci-direct.h>
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#include <asm/io.h>
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#include <asm/paravirt.h>
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#include <asm/setup.h>
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#define TOPOLOGY_REGISTER_OFFSET 0x10
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#ifdef CONFIG_PCI
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static void __init set_vsmp_ctl(void)
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{
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void __iomem *address;
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unsigned int cap, ctl, cfg;
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/* set vSMP magic bits to indicate vSMP capable kernel */
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cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
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address = early_ioremap(cfg, 8);
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cap = readl(address);
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ctl = readl(address + 4);
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printk(KERN_INFO "vSMP CTL: capabilities:0x%08x control:0x%08x\n",
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cap, ctl);
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/* If possible, let the vSMP foundation route the interrupt optimally */
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#ifdef CONFIG_SMP
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if (cap & ctl & BIT(8)) {
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ctl &= ~BIT(8);
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#ifdef CONFIG_PROC_FS
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/* Don't let users change irq affinity via procfs */
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no_irq_affinity = 1;
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#endif
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}
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#endif
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writel(ctl, address + 4);
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ctl = readl(address + 4);
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pr_info("vSMP CTL: control set to:0x%08x\n", ctl);
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early_iounmap(address, 8);
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}
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static int is_vsmp = -1;
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static void __init detect_vsmp_box(void)
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{
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is_vsmp = 0;
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if (!early_pci_allowed())
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return;
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/* Check if we are running on a ScaleMP vSMPowered box */
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if (read_pci_config(0, 0x1f, 0, PCI_VENDOR_ID) ==
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(PCI_VENDOR_ID_SCALEMP | (PCI_DEVICE_ID_SCALEMP_VSMP_CTL << 16)))
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is_vsmp = 1;
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}
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static int is_vsmp_box(void)
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{
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if (is_vsmp != -1)
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return is_vsmp;
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else {
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WARN_ON_ONCE(1);
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return 0;
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}
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}
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#else
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static void __init detect_vsmp_box(void)
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{
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}
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static int is_vsmp_box(void)
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{
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return 0;
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}
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static void __init set_vsmp_ctl(void)
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{
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}
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#endif
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static void __init vsmp_cap_cpus(void)
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{
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#if !defined(CONFIG_X86_VSMP) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
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void __iomem *address;
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unsigned int cfg, topology, node_shift, maxcpus;
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/*
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* CONFIG_X86_VSMP is not configured, so limit the number CPUs to the
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* ones present in the first board, unless explicitly overridden by
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* setup_max_cpus
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*/
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if (setup_max_cpus != NR_CPUS)
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return;
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/* Read the vSMP Foundation topology register */
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cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
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address = early_ioremap(cfg + TOPOLOGY_REGISTER_OFFSET, 4);
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if (WARN_ON(!address))
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return;
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topology = readl(address);
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node_shift = (topology >> 16) & 0x7;
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if (!node_shift)
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/* The value 0 should be decoded as 8 */
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node_shift = 8;
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maxcpus = (topology & ((1 << node_shift) - 1)) + 1;
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pr_info("vSMP CTL: Capping CPUs to %d (CONFIG_X86_VSMP is unset)\n",
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maxcpus);
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setup_max_cpus = maxcpus;
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early_iounmap(address, 4);
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#endif
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}
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static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
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{
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return hard_smp_processor_id() >> index_msb;
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}
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static void vsmp_apic_post_init(void)
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{
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/* need to update phys_pkg_id */
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apic->phys_pkg_id = apicid_phys_pkg_id;
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}
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void __init vsmp_init(void)
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{
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detect_vsmp_box();
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if (!is_vsmp_box())
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return;
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x86_platform.apic_post_init = vsmp_apic_post_init;
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vsmp_cap_cpus();
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set_vsmp_ctl();
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return;
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}
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