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05780d9808
Several files refer to an old address for the Free Software Foundation in the file header comment. Resolve by replacing the address with the URL <http://www.gnu.org/licenses/> so that we do not have to keep updating the header comments anytime the address changes. CC: Wolfgang Grandegger <wg@grandegger.com> CC: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
304 lines
9.5 KiB
C
304 lines
9.5 KiB
C
/*
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* Definitions of consts/structs to drive the Freescale MSCAN.
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*
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* Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
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* Varma Electronics Oy
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the version 2 of the GNU General Public License
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSCAN_H__
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#define __MSCAN_H__
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#include <linux/clk.h>
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#include <linux/types.h>
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/* MSCAN control register 0 (CANCTL0) bits */
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#define MSCAN_RXFRM 0x80
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#define MSCAN_RXACT 0x40
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#define MSCAN_CSWAI 0x20
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#define MSCAN_SYNCH 0x10
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#define MSCAN_TIME 0x08
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#define MSCAN_WUPE 0x04
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#define MSCAN_SLPRQ 0x02
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#define MSCAN_INITRQ 0x01
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/* MSCAN control register 1 (CANCTL1) bits */
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#define MSCAN_CANE 0x80
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#define MSCAN_CLKSRC 0x40
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#define MSCAN_LOOPB 0x20
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#define MSCAN_LISTEN 0x10
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#define MSCAN_BORM 0x08
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#define MSCAN_WUPM 0x04
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#define MSCAN_SLPAK 0x02
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#define MSCAN_INITAK 0x01
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/* Use the MPC5XXX MSCAN variant? */
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#ifdef CONFIG_PPC
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#define MSCAN_FOR_MPC5XXX
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#endif
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#ifdef MSCAN_FOR_MPC5XXX
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#define MSCAN_CLKSRC_BUS 0
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#define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
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#define MSCAN_CLKSRC_IPS MSCAN_CLKSRC
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#else
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#define MSCAN_CLKSRC_BUS MSCAN_CLKSRC
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#define MSCAN_CLKSRC_XTAL 0
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#endif
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/* MSCAN receiver flag register (CANRFLG) bits */
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#define MSCAN_WUPIF 0x80
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#define MSCAN_CSCIF 0x40
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#define MSCAN_RSTAT1 0x20
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#define MSCAN_RSTAT0 0x10
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#define MSCAN_TSTAT1 0x08
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#define MSCAN_TSTAT0 0x04
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#define MSCAN_OVRIF 0x02
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#define MSCAN_RXF 0x01
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#define MSCAN_ERR_IF (MSCAN_OVRIF | MSCAN_CSCIF)
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#define MSCAN_RSTAT_MSK (MSCAN_RSTAT1 | MSCAN_RSTAT0)
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#define MSCAN_TSTAT_MSK (MSCAN_TSTAT1 | MSCAN_TSTAT0)
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#define MSCAN_STAT_MSK (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
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#define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
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MSCAN_TSTAT1 | MSCAN_TSTAT0)
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#define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
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#define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
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#define MSCAN_STATE_ACTIVE 0
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#define MSCAN_STATE_WARNING 1
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#define MSCAN_STATE_PASSIVE 2
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#define MSCAN_STATE_BUSOFF 3
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/* MSCAN receiver interrupt enable register (CANRIER) bits */
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#define MSCAN_WUPIE 0x80
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#define MSCAN_CSCIE 0x40
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#define MSCAN_RSTATE1 0x20
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#define MSCAN_RSTATE0 0x10
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#define MSCAN_TSTATE1 0x08
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#define MSCAN_TSTATE0 0x04
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#define MSCAN_OVRIE 0x02
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#define MSCAN_RXFIE 0x01
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/* MSCAN transmitter flag register (CANTFLG) bits */
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#define MSCAN_TXE2 0x04
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#define MSCAN_TXE1 0x02
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#define MSCAN_TXE0 0x01
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#define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
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/* MSCAN transmitter interrupt enable register (CANTIER) bits */
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#define MSCAN_TXIE2 0x04
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#define MSCAN_TXIE1 0x02
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#define MSCAN_TXIE0 0x01
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#define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
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/* MSCAN transmitter message abort request (CANTARQ) bits */
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#define MSCAN_ABTRQ2 0x04
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#define MSCAN_ABTRQ1 0x02
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#define MSCAN_ABTRQ0 0x01
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/* MSCAN transmitter message abort ack (CANTAAK) bits */
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#define MSCAN_ABTAK2 0x04
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#define MSCAN_ABTAK1 0x02
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#define MSCAN_ABTAK0 0x01
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/* MSCAN transmit buffer selection (CANTBSEL) bits */
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#define MSCAN_TX2 0x04
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#define MSCAN_TX1 0x02
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#define MSCAN_TX0 0x01
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/* MSCAN ID acceptance control register (CANIDAC) bits */
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#define MSCAN_IDAM1 0x20
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#define MSCAN_IDAM0 0x10
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#define MSCAN_IDHIT2 0x04
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#define MSCAN_IDHIT1 0x02
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#define MSCAN_IDHIT0 0x01
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#define MSCAN_AF_32BIT 0x00
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#define MSCAN_AF_16BIT MSCAN_IDAM0
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#define MSCAN_AF_8BIT MSCAN_IDAM1
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#define MSCAN_AF_CLOSED (MSCAN_IDAM0|MSCAN_IDAM1)
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#define MSCAN_AF_MASK (~(MSCAN_IDAM0|MSCAN_IDAM1))
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/* MSCAN Miscellaneous Register (CANMISC) bits */
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#define MSCAN_BOHOLD 0x01
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/* MSCAN Identifier Register (IDR) bits */
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#define MSCAN_SFF_RTR_SHIFT 4
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#define MSCAN_EFF_RTR_SHIFT 0
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#define MSCAN_EFF_FLAGS 0x18 /* IDE + SRR */
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#ifdef MSCAN_FOR_MPC5XXX
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#define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
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#define _MSCAN_RESERVED_DSR_SIZE 2
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#else
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#define _MSCAN_RESERVED_(n, num)
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#define _MSCAN_RESERVED_DSR_SIZE 0
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#endif
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/* Structure of the hardware registers */
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struct mscan_regs {
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/* (see doc S12MSCANV3/D) MPC5200 MSCAN */
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u8 canctl0; /* + 0x00 0x00 */
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u8 canctl1; /* + 0x01 0x01 */
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_MSCAN_RESERVED_(1, 2); /* + 0x02 */
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u8 canbtr0; /* + 0x04 0x02 */
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u8 canbtr1; /* + 0x05 0x03 */
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_MSCAN_RESERVED_(2, 2); /* + 0x06 */
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u8 canrflg; /* + 0x08 0x04 */
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u8 canrier; /* + 0x09 0x05 */
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_MSCAN_RESERVED_(3, 2); /* + 0x0a */
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u8 cantflg; /* + 0x0c 0x06 */
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u8 cantier; /* + 0x0d 0x07 */
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_MSCAN_RESERVED_(4, 2); /* + 0x0e */
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u8 cantarq; /* + 0x10 0x08 */
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u8 cantaak; /* + 0x11 0x09 */
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_MSCAN_RESERVED_(5, 2); /* + 0x12 */
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u8 cantbsel; /* + 0x14 0x0a */
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u8 canidac; /* + 0x15 0x0b */
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u8 reserved; /* + 0x16 0x0c */
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_MSCAN_RESERVED_(6, 2); /* + 0x17 */
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u8 canmisc; /* + 0x19 0x0d */
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_MSCAN_RESERVED_(7, 2); /* + 0x1a */
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u8 canrxerr; /* + 0x1c 0x0e */
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u8 cantxerr; /* + 0x1d 0x0f */
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_MSCAN_RESERVED_(8, 2); /* + 0x1e */
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u16 canidar1_0; /* + 0x20 0x10 */
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_MSCAN_RESERVED_(9, 2); /* + 0x22 */
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u16 canidar3_2; /* + 0x24 0x12 */
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_MSCAN_RESERVED_(10, 2); /* + 0x26 */
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u16 canidmr1_0; /* + 0x28 0x14 */
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_MSCAN_RESERVED_(11, 2); /* + 0x2a */
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u16 canidmr3_2; /* + 0x2c 0x16 */
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_MSCAN_RESERVED_(12, 2); /* + 0x2e */
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u16 canidar5_4; /* + 0x30 0x18 */
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_MSCAN_RESERVED_(13, 2); /* + 0x32 */
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u16 canidar7_6; /* + 0x34 0x1a */
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_MSCAN_RESERVED_(14, 2); /* + 0x36 */
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u16 canidmr5_4; /* + 0x38 0x1c */
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_MSCAN_RESERVED_(15, 2); /* + 0x3a */
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u16 canidmr7_6; /* + 0x3c 0x1e */
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_MSCAN_RESERVED_(16, 2); /* + 0x3e */
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struct {
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u16 idr1_0; /* + 0x40 0x20 */
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_MSCAN_RESERVED_(17, 2); /* + 0x42 */
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u16 idr3_2; /* + 0x44 0x22 */
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_MSCAN_RESERVED_(18, 2); /* + 0x46 */
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u16 dsr1_0; /* + 0x48 0x24 */
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_MSCAN_RESERVED_(19, 2); /* + 0x4a */
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u16 dsr3_2; /* + 0x4c 0x26 */
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_MSCAN_RESERVED_(20, 2); /* + 0x4e */
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u16 dsr5_4; /* + 0x50 0x28 */
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_MSCAN_RESERVED_(21, 2); /* + 0x52 */
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u16 dsr7_6; /* + 0x54 0x2a */
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_MSCAN_RESERVED_(22, 2); /* + 0x56 */
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u8 dlr; /* + 0x58 0x2c */
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u8 reserved; /* + 0x59 0x2d */
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_MSCAN_RESERVED_(23, 2); /* + 0x5a */
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u16 time; /* + 0x5c 0x2e */
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} rx;
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_MSCAN_RESERVED_(24, 2); /* + 0x5e */
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struct {
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u16 idr1_0; /* + 0x60 0x30 */
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_MSCAN_RESERVED_(25, 2); /* + 0x62 */
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u16 idr3_2; /* + 0x64 0x32 */
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_MSCAN_RESERVED_(26, 2); /* + 0x66 */
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u16 dsr1_0; /* + 0x68 0x34 */
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_MSCAN_RESERVED_(27, 2); /* + 0x6a */
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u16 dsr3_2; /* + 0x6c 0x36 */
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_MSCAN_RESERVED_(28, 2); /* + 0x6e */
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u16 dsr5_4; /* + 0x70 0x38 */
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_MSCAN_RESERVED_(29, 2); /* + 0x72 */
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u16 dsr7_6; /* + 0x74 0x3a */
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_MSCAN_RESERVED_(30, 2); /* + 0x76 */
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u8 dlr; /* + 0x78 0x3c */
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u8 tbpr; /* + 0x79 0x3d */
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_MSCAN_RESERVED_(31, 2); /* + 0x7a */
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u16 time; /* + 0x7c 0x3e */
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} tx;
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_MSCAN_RESERVED_(32, 2); /* + 0x7e */
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} __packed;
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#undef _MSCAN_RESERVED_
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#define MSCAN_REGION sizeof(struct mscan)
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#define MSCAN_NORMAL_MODE 0
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#define MSCAN_SLEEP_MODE MSCAN_SLPRQ
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#define MSCAN_INIT_MODE (MSCAN_INITRQ | MSCAN_SLPRQ)
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#define MSCAN_POWEROFF_MODE (MSCAN_CSWAI | MSCAN_SLPRQ)
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#define MSCAN_SET_MODE_RETRIES 255
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#define MSCAN_ECHO_SKB_MAX 3
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#define MSCAN_RX_INTS_ENABLE (MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | \
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MSCAN_RSTATE1 | MSCAN_RSTATE0 | \
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MSCAN_TSTATE1 | MSCAN_TSTATE0)
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/* MSCAN type variants */
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enum {
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MSCAN_TYPE_MPC5200,
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MSCAN_TYPE_MPC5121
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};
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#define BTR0_BRP_MASK 0x3f
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#define BTR0_SJW_SHIFT 6
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#define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT)
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#define BTR1_TSEG1_MASK 0xf
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#define BTR1_TSEG2_SHIFT 4
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#define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT)
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#define BTR1_SAM_SHIFT 7
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#define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK)
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#define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
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BTR0_SJW_MASK)
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#define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK)
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#define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
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BTR1_TSEG2_MASK)
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#define BTR1_SET_SAM(sam) ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
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#define F_RX_PROGRESS 0
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#define F_TX_PROGRESS 1
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#define F_TX_WAIT_ALL 2
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#define TX_QUEUE_SIZE 3
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struct tx_queue_entry {
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struct list_head list;
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u8 mask;
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u8 id;
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};
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struct mscan_priv {
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struct can_priv can; /* must be the first member */
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unsigned int type; /* MSCAN type variants */
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unsigned long flags;
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void __iomem *reg_base; /* ioremap'ed address to registers */
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struct clk *clk_ipg; /* clock for registers */
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struct clk *clk_can; /* clock for bitrates */
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u8 shadow_statflg;
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u8 shadow_canrier;
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u8 cur_pri;
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u8 prev_buf_id;
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u8 tx_active;
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struct list_head tx_head;
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struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
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struct napi_struct napi;
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};
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struct net_device *alloc_mscandev(void);
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int register_mscandev(struct net_device *dev, int mscan_clksrc);
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void unregister_mscandev(struct net_device *dev);
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#endif /* __MSCAN_H__ */
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