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7d49efe2ed
- Secondary CPUs entry endianness fix - Make NR_CPUS default to 8 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iQIcBAABAgAGBQJSogkcAAoJEGvWsS0AyF7xJz0P/RQ8J+Lt5/q2U/9QOAQ97+rd U/oqrQ7HThgo+w+YJtG24OCVcYfmwmqVIsawF7IvzCcNQLZYe1EoowQ4T8/jrc3d FUlQMKjRJdoolhv1SZ9rtdkbMQXuRwpC3lcD8TOvYxjdAHnK8SKVwv+yBmIyYGsJ BqX46ZAHHuDkQV66doZfIcyoXJv0uJp+p1yfGSH0KKPXMMYqxYdSwqR5mo+m6Zem UT4k9M8VpE2E8ALYVyTuJlXuQQ4bSXkhRzdb7ewk5ArhAn/x+Py+TlHhs364ezQq bohXRP/Kb7maEUlUYC1RTD4RkWeh5iTtIRJhW19KJS4Im7NHF9m0EDDYS9tU8CCi XpRS6CGW6bebxBz/Rg1P8sn0YcbWuwNu143if7oBwkNqzdzjiR+rjH+VtKHJdl6A +goRowx2AbEGcc5Syii8se49/jIIbwY44viefv/VaIc7WOOlx6jXiDWZZ4LzBHXb CO/WPrblaqi7dnP97EgbFn9jBrY+MN8xRAoD5sliGMzQlq9rcyauArmMxpKUZk+r yOCe9PD4t9bjjRONtj1ea0KAfWv9K2UsJLUt7v7oTPVnI12Mq0EXU9Vxj+xLNSM9 1idzda/7OMwQ6UrZiMHdb7gFSi0GObMjEsjAlMZRAr4DuIkLoRjoKlSxZmzYLROs poPwiv09bS/9u213KWL7 =3yQ/ -----END PGP SIGNATURE----- Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull ARM64 fixes from Catalin Marinas: - Page table fixes (PROT_NONE, shareability attribute, TLB invalidation) - Secondary CPUs entry endianness fix - Make NR_CPUS default to 8 * tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: mm: Fix PMD_SECT_PROT_NONE definition arm64: Fix memory shareability attribute for ioremap_wc/cache arm64: kernel: add code to set cpu boot mode to secondary_entry shim arm64: make default NR_CPUS 8 arm64: ensure completion of TLB invalidatation |
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Kconfig |