Thomas Gleixner 7f049fbdd5 perf/x86/intel/lbr: Zero the xstate buffer on allocation ... XRSTORS requires a valid xstate buffer to work correctly. XSAVES does not guarantee to write a fully valid buffer according to the SDM: "XSAVES does not write to any parts of the XSAVE header other than the XSTATE_BV and XCOMP_BV fields." XRSTORS triggers a #GP: "If bytes 63:16 of the XSAVE header are not all zero." It's dubious at best how this can work at all when the buffer is not zeroed before use. Allocate the buffers with __GFP_ZERO to prevent XRSTORS failure. Fixes: ce711ea3ca ("perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/87wnr0wo2z.ffs@nanos.tec.linutronix.de		2021-06-24 08:49:03 +02:00
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amd	Handle power-gating of AMD IOMMU perf counters properly when they are used.	2021-05-09 13:00:26 -07:00
intel	perf/x86/intel/lbr: Zero the xstate buffer on allocation	2021-06-24 08:49:03 +02:00
zhaoxin	x86: Fix various typos in comments	2021-03-18 15:31:53 +01:00
core.c	perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context	2021-05-18 12:53:47 +02:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Alder Lake CPU support	2021-04-19 20:03:29 +02:00
perf_event.h	perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context	2021-05-18 12:53:47 +02:00
probe.c	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
probe.h	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
rapl.c	perf/x86/rapl: Add support for Intel Alder Lake	2021-04-19 20:03:30 +02:00