mirror of
https://github.com/edk2-porting/linux-next.git
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7be2958e97
Add runtime PM support to the ARM PMU driver so that devices such as OMAP supporting dynamic PM can use the platform->runtime_* hooks to initialise hardware at runtime. Without having these runtime PM hooks in place any configuration of the PMU hardware would be lost when low power states are entered and hence would prevent PMU from working. This change also replaces the PMU platform functions enable_irq and disable_irq added by Ming Lei with runtime_resume and runtime_suspend funtions. Ming had added the enable_irq and disable_irq functions as a method to configure the cross trigger interface on OMAP4 for routing the PMU interrupts. By adding runtime PM support, we can move the code called by enable_irq and disable_irq into the runtime PM callbacks runtime_resume and runtime_suspend. Cc: Ming Lei <ming.lei@canonical.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
878 lines
21 KiB
C
878 lines
21 KiB
C
#undef DEBUG
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/*
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* ARM performance counter support.
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*
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* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
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* Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
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*
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* This code is based on the sparc64 perf event code, which is in turn based
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* on the x86 code. Callchain code is based on the ARM OProfile backtrace
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* code.
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*/
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#define pr_fmt(fmt) "hw perfevents: " fmt
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#include <linux/bitmap.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <linux/pm_runtime.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/pmu.h>
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#include <asm/stacktrace.h>
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/*
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* ARMv6 supports a maximum of 3 events, starting from index 0. If we add
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* another platform that supports more, we need to increase this to be the
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* largest of all platforms.
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*
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* ARMv7 supports up to 32 events:
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* cycle counter CCNT + 31 events counters CNT0..30.
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* Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
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*/
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#define ARMPMU_MAX_HWEVENTS 32
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static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
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static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
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static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
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#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
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/* Set at runtime when we know what CPU type we are. */
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static struct arm_pmu *cpu_pmu;
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const char *perf_pmu_name(void)
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{
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if (!cpu_pmu)
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return NULL;
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return cpu_pmu->pmu.name;
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}
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EXPORT_SYMBOL_GPL(perf_pmu_name);
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int perf_num_counters(void)
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{
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int max_events = 0;
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if (cpu_pmu != NULL)
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max_events = cpu_pmu->num_events;
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return max_events;
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}
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EXPORT_SYMBOL_GPL(perf_num_counters);
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#define HW_OP_UNSUPPORTED 0xFFFF
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#define C(_x) \
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PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xFFFF
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static int
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armpmu_map_cache_event(const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u64 config)
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{
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unsigned int cache_type, cache_op, cache_result, ret;
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cache_type = (config >> 0) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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cache_op = (config >> 8) & 0xff;
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if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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return -EINVAL;
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cache_result = (config >> 16) & 0xff;
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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return ret;
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}
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static int
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armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
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{
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int mapping = (*event_map)[config];
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return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
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}
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static int
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armpmu_map_raw_event(u32 raw_event_mask, u64 config)
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{
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return (int)(config & raw_event_mask);
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}
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static int map_cpu_event(struct perf_event *event,
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const unsigned (*event_map)[PERF_COUNT_HW_MAX],
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const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u32 raw_event_mask)
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{
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u64 config = event->attr.config;
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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return armpmu_map_event(event_map, config);
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case PERF_TYPE_HW_CACHE:
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return armpmu_map_cache_event(cache_map, config);
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case PERF_TYPE_RAW:
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return armpmu_map_raw_event(raw_event_mask, config);
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}
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return -ENOENT;
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}
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int
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armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (left > (s64)armpmu->max_period)
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left = armpmu->max_period;
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local64_set(&hwc->prev_count, (u64)-left);
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armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
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perf_event_update_userpage(event);
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return ret;
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}
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u64
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armpmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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u64 delta, prev_raw_count, new_raw_count;
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = armpmu->read_counter(idx);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return new_raw_count;
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}
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static void
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armpmu_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* Don't read disabled counters! */
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if (hwc->idx < 0)
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return;
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armpmu_event_update(event, hwc, hwc->idx);
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}
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static void
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armpmu_stop(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* ARM pmu always has to update the counter, so ignore
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* PERF_EF_UPDATE, see comments in armpmu_start().
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*/
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if (!(hwc->state & PERF_HES_STOPPED)) {
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armpmu->disable(hwc, hwc->idx);
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barrier(); /* why? */
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armpmu_event_update(event, hwc, hwc->idx);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static void
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armpmu_start(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* ARM pmu always has to reprogram the period, so ignore
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* PERF_EF_RELOAD, see the comment below.
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*/
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/*
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* Set the period again. Some counters can't be stopped, so when we
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* were stopped we simply disabled the IRQ source and the counter
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* may have been left counting. If we don't do this step then we may
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* get an interrupt too soon or *way* too late if the overflow has
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* happened since disabling.
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*/
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armpmu_event_set_period(event, hwc, hwc->idx);
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armpmu->enable(hwc, hwc->idx);
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}
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static void
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armpmu_del(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *hw_events = armpmu->get_hw_events();
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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WARN_ON(idx < 0);
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armpmu_stop(event, PERF_EF_UPDATE);
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hw_events->events[idx] = NULL;
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clear_bit(idx, hw_events->used_mask);
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perf_event_update_userpage(event);
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}
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static int
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armpmu_add(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *hw_events = armpmu->get_hw_events();
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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int err = 0;
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perf_pmu_disable(event->pmu);
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/* If we don't have a space for the counter then finish early. */
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idx = armpmu->get_event_idx(hw_events, hwc);
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if (idx < 0) {
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err = idx;
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goto out;
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}
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/*
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* If there is an event in the counter we are going to use then make
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* sure it is disabled.
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*/
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event->hw.idx = idx;
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armpmu->disable(hwc, idx);
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hw_events->events[idx] = event;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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armpmu_start(event, PERF_EF_RELOAD);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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out:
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perf_pmu_enable(event->pmu);
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return err;
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}
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static int
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validate_event(struct pmu_hw_events *hw_events,
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struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event fake_event = event->hw;
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struct pmu *leader_pmu = event->group_leader->pmu;
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if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
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return 1;
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return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
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}
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static int
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validate_group(struct perf_event *event)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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struct pmu_hw_events fake_pmu;
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DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
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/*
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* Initialise the fake PMU. We only need to populate the
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* used_mask for the purposes of validation.
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*/
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memset(fake_used_mask, 0, sizeof(fake_used_mask));
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fake_pmu.used_mask = fake_used_mask;
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if (!validate_event(&fake_pmu, leader))
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return -EINVAL;
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list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
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if (!validate_event(&fake_pmu, sibling))
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return -EINVAL;
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}
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if (!validate_event(&fake_pmu, event))
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return -EINVAL;
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return 0;
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}
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static irqreturn_t armpmu_platform_irq(int irq, void *dev)
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{
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struct arm_pmu *armpmu = (struct arm_pmu *) dev;
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struct platform_device *plat_device = armpmu->plat_device;
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struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
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return plat->handle_irq(irq, dev, armpmu->handle_irq);
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}
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static void
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armpmu_release_hardware(struct arm_pmu *armpmu)
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{
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int i, irq, irqs;
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struct platform_device *pmu_device = armpmu->plat_device;
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irqs = min(pmu_device->num_resources, num_possible_cpus());
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for (i = 0; i < irqs; ++i) {
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if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
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continue;
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, armpmu);
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}
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pm_runtime_put_sync(&pmu_device->dev);
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release_pmu(armpmu->type);
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}
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static int
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armpmu_reserve_hardware(struct arm_pmu *armpmu)
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{
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struct arm_pmu_platdata *plat;
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irq_handler_t handle_irq;
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int i, err, irq, irqs;
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struct platform_device *pmu_device = armpmu->plat_device;
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if (!pmu_device)
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return -ENODEV;
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err = reserve_pmu(armpmu->type);
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if (err) {
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pr_warning("unable to reserve pmu\n");
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return err;
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}
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plat = dev_get_platdata(&pmu_device->dev);
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if (plat && plat->handle_irq)
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handle_irq = armpmu_platform_irq;
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else
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handle_irq = armpmu->handle_irq;
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irqs = min(pmu_device->num_resources, num_possible_cpus());
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if (irqs < 1) {
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pr_err("no irqs for PMUs defined\n");
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return -ENODEV;
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}
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pm_runtime_get_sync(&pmu_device->dev);
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for (i = 0; i < irqs; ++i) {
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err = 0;
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irq = platform_get_irq(pmu_device, i);
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if (irq < 0)
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continue;
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/*
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* If we have a single PMU interrupt that we can't shift,
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* assume that we're running on a uniprocessor machine and
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* continue. Otherwise, continue without this interrupt.
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*/
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if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
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pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
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irq, i);
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continue;
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}
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err = request_irq(irq, handle_irq,
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IRQF_DISABLED | IRQF_NOBALANCING,
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"arm-pmu", armpmu);
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if (err) {
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pr_err("unable to request IRQ%d for ARM PMU counters\n",
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irq);
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armpmu_release_hardware(armpmu);
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return err;
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}
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cpumask_set_cpu(i, &armpmu->active_irqs);
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}
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return 0;
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}
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static void
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hw_perf_event_destroy(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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atomic_t *active_events = &armpmu->active_events;
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struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
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if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
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armpmu_release_hardware(armpmu);
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mutex_unlock(pmu_reserve_mutex);
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}
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}
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static int
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event_requires_mode_exclusion(struct perf_event_attr *attr)
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{
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return attr->exclude_idle || attr->exclude_user ||
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attr->exclude_kernel || attr->exclude_hv;
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}
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static int
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__hw_perf_event_init(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int mapping, err;
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mapping = armpmu->map_event(event);
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if (mapping < 0) {
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pr_debug("event %x:%llx not supported\n", event->attr.type,
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event->attr.config);
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return mapping;
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}
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/*
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet. For SMP systems, each core has it's own PMU so we can't do any
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* clever allocation or constraints checking at this point.
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*/
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hwc->idx = -1;
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hwc->config_base = 0;
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hwc->config = 0;
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hwc->event_base = 0;
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/*
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* Check whether we need to exclude the counter from certain modes.
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*/
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if ((!armpmu->set_event_filter ||
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armpmu->set_event_filter(hwc, &event->attr)) &&
|
|
event_requires_mode_exclusion(&event->attr)) {
|
|
pr_debug("ARM performance counters do not support "
|
|
"mode exclusion\n");
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
/*
|
|
* Store the event encoding into the config_base field.
|
|
*/
|
|
hwc->config_base |= (unsigned long)mapping;
|
|
|
|
if (!hwc->sample_period) {
|
|
/*
|
|
* For non-sampling runs, limit the sample_period to half
|
|
* of the counter width. That way, the new counter value
|
|
* is far less likely to overtake the previous one unless
|
|
* you have some serious IRQ latency issues.
|
|
*/
|
|
hwc->sample_period = armpmu->max_period >> 1;
|
|
hwc->last_period = hwc->sample_period;
|
|
local64_set(&hwc->period_left, hwc->sample_period);
|
|
}
|
|
|
|
err = 0;
|
|
if (event->group_leader != event) {
|
|
err = validate_group(event);
|
|
if (err)
|
|
return -EINVAL;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int armpmu_event_init(struct perf_event *event)
|
|
{
|
|
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
|
|
int err = 0;
|
|
atomic_t *active_events = &armpmu->active_events;
|
|
|
|
/* does not support taken branch sampling */
|
|
if (has_branch_stack(event))
|
|
return -EOPNOTSUPP;
|
|
|
|
if (armpmu->map_event(event) == -ENOENT)
|
|
return -ENOENT;
|
|
|
|
event->destroy = hw_perf_event_destroy;
|
|
|
|
if (!atomic_inc_not_zero(active_events)) {
|
|
mutex_lock(&armpmu->reserve_mutex);
|
|
if (atomic_read(active_events) == 0)
|
|
err = armpmu_reserve_hardware(armpmu);
|
|
|
|
if (!err)
|
|
atomic_inc(active_events);
|
|
mutex_unlock(&armpmu->reserve_mutex);
|
|
}
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
err = __hw_perf_event_init(event);
|
|
if (err)
|
|
hw_perf_event_destroy(event);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void armpmu_enable(struct pmu *pmu)
|
|
{
|
|
struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
|
struct pmu_hw_events *hw_events = armpmu->get_hw_events();
|
|
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
|
|
|
if (enabled)
|
|
armpmu->start();
|
|
}
|
|
|
|
static void armpmu_disable(struct pmu *pmu)
|
|
{
|
|
struct arm_pmu *armpmu = to_arm_pmu(pmu);
|
|
armpmu->stop();
|
|
}
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
static int armpmu_runtime_resume(struct device *dev)
|
|
{
|
|
struct arm_pmu_platdata *plat = dev_get_platdata(dev);
|
|
|
|
if (plat && plat->runtime_resume)
|
|
return plat->runtime_resume(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int armpmu_runtime_suspend(struct device *dev)
|
|
{
|
|
struct arm_pmu_platdata *plat = dev_get_platdata(dev);
|
|
|
|
if (plat && plat->runtime_suspend)
|
|
return plat->runtime_suspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void __init armpmu_init(struct arm_pmu *armpmu)
|
|
{
|
|
atomic_set(&armpmu->active_events, 0);
|
|
mutex_init(&armpmu->reserve_mutex);
|
|
|
|
armpmu->pmu = (struct pmu) {
|
|
.pmu_enable = armpmu_enable,
|
|
.pmu_disable = armpmu_disable,
|
|
.event_init = armpmu_event_init,
|
|
.add = armpmu_add,
|
|
.del = armpmu_del,
|
|
.start = armpmu_start,
|
|
.stop = armpmu_stop,
|
|
.read = armpmu_read,
|
|
};
|
|
}
|
|
|
|
int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
|
|
{
|
|
armpmu_init(armpmu);
|
|
return perf_pmu_register(&armpmu->pmu, name, type);
|
|
}
|
|
|
|
/* Include the PMU-specific implementations. */
|
|
#include "perf_event_xscale.c"
|
|
#include "perf_event_v6.c"
|
|
#include "perf_event_v7.c"
|
|
|
|
/*
|
|
* Ensure the PMU has sane values out of reset.
|
|
* This requires SMP to be available, so exists as a separate initcall.
|
|
*/
|
|
static int __init
|
|
cpu_pmu_reset(void)
|
|
{
|
|
if (cpu_pmu && cpu_pmu->reset)
|
|
return on_each_cpu(cpu_pmu->reset, NULL, 1);
|
|
return 0;
|
|
}
|
|
arch_initcall(cpu_pmu_reset);
|
|
|
|
/*
|
|
* PMU platform driver and devicetree bindings.
|
|
*/
|
|
static struct of_device_id armpmu_of_device_ids[] = {
|
|
{.compatible = "arm,cortex-a9-pmu"},
|
|
{.compatible = "arm,cortex-a8-pmu"},
|
|
{.compatible = "arm,arm1136-pmu"},
|
|
{.compatible = "arm,arm1176-pmu"},
|
|
{},
|
|
};
|
|
|
|
static struct platform_device_id armpmu_plat_device_ids[] = {
|
|
{.name = "arm-pmu"},
|
|
{},
|
|
};
|
|
|
|
static int __devinit armpmu_device_probe(struct platform_device *pdev)
|
|
{
|
|
if (!cpu_pmu)
|
|
return -ENODEV;
|
|
|
|
cpu_pmu->plat_device = pdev;
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops armpmu_dev_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver armpmu_driver = {
|
|
.driver = {
|
|
.name = "arm-pmu",
|
|
.pm = &armpmu_dev_pm_ops,
|
|
.of_match_table = armpmu_of_device_ids,
|
|
},
|
|
.probe = armpmu_device_probe,
|
|
.id_table = armpmu_plat_device_ids,
|
|
};
|
|
|
|
static int __init register_pmu_driver(void)
|
|
{
|
|
return platform_driver_register(&armpmu_driver);
|
|
}
|
|
device_initcall(register_pmu_driver);
|
|
|
|
static struct pmu_hw_events *armpmu_get_cpu_events(void)
|
|
{
|
|
return &__get_cpu_var(cpu_hw_events);
|
|
}
|
|
|
|
static void __init cpu_pmu_init(struct arm_pmu *armpmu)
|
|
{
|
|
int cpu;
|
|
for_each_possible_cpu(cpu) {
|
|
struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
|
|
events->events = per_cpu(hw_events, cpu);
|
|
events->used_mask = per_cpu(used_mask, cpu);
|
|
raw_spin_lock_init(&events->pmu_lock);
|
|
}
|
|
armpmu->get_hw_events = armpmu_get_cpu_events;
|
|
armpmu->type = ARM_PMU_DEVICE_CPU;
|
|
}
|
|
|
|
/*
|
|
* PMU hardware loses all context when a CPU goes offline.
|
|
* When a CPU is hotplugged back in, since some hardware registers are
|
|
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
|
|
* junk values out of them.
|
|
*/
|
|
static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
|
|
return NOTIFY_DONE;
|
|
|
|
if (cpu_pmu && cpu_pmu->reset)
|
|
cpu_pmu->reset(NULL);
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
|
|
.notifier_call = pmu_cpu_notify,
|
|
};
|
|
|
|
/*
|
|
* CPU PMU identification and registration.
|
|
*/
|
|
static int __init
|
|
init_hw_perf_events(void)
|
|
{
|
|
unsigned long cpuid = read_cpuid_id();
|
|
unsigned long implementor = (cpuid & 0xFF000000) >> 24;
|
|
unsigned long part_number = (cpuid & 0xFFF0);
|
|
|
|
/* ARM Ltd CPUs. */
|
|
if (0x41 == implementor) {
|
|
switch (part_number) {
|
|
case 0xB360: /* ARM1136 */
|
|
case 0xB560: /* ARM1156 */
|
|
case 0xB760: /* ARM1176 */
|
|
cpu_pmu = armv6pmu_init();
|
|
break;
|
|
case 0xB020: /* ARM11mpcore */
|
|
cpu_pmu = armv6mpcore_pmu_init();
|
|
break;
|
|
case 0xC080: /* Cortex-A8 */
|
|
cpu_pmu = armv7_a8_pmu_init();
|
|
break;
|
|
case 0xC090: /* Cortex-A9 */
|
|
cpu_pmu = armv7_a9_pmu_init();
|
|
break;
|
|
case 0xC050: /* Cortex-A5 */
|
|
cpu_pmu = armv7_a5_pmu_init();
|
|
break;
|
|
case 0xC0F0: /* Cortex-A15 */
|
|
cpu_pmu = armv7_a15_pmu_init();
|
|
break;
|
|
case 0xC070: /* Cortex-A7 */
|
|
cpu_pmu = armv7_a7_pmu_init();
|
|
break;
|
|
}
|
|
/* Intel CPUs [xscale]. */
|
|
} else if (0x69 == implementor) {
|
|
part_number = (cpuid >> 13) & 0x7;
|
|
switch (part_number) {
|
|
case 1:
|
|
cpu_pmu = xscale1pmu_init();
|
|
break;
|
|
case 2:
|
|
cpu_pmu = xscale2pmu_init();
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (cpu_pmu) {
|
|
pr_info("enabled with %s PMU driver, %d counters available\n",
|
|
cpu_pmu->name, cpu_pmu->num_events);
|
|
cpu_pmu_init(cpu_pmu);
|
|
register_cpu_notifier(&pmu_cpu_notifier);
|
|
armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
|
|
} else {
|
|
pr_info("no hardware support available\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(init_hw_perf_events);
|
|
|
|
/*
|
|
* Callchain handling code.
|
|
*/
|
|
|
|
/*
|
|
* The registers we're interested in are at the end of the variable
|
|
* length saved register structure. The fp points at the end of this
|
|
* structure so the address of this struct is:
|
|
* (struct frame_tail *)(xxx->fp)-1
|
|
*
|
|
* This code has been adapted from the ARM OProfile support.
|
|
*/
|
|
struct frame_tail {
|
|
struct frame_tail __user *fp;
|
|
unsigned long sp;
|
|
unsigned long lr;
|
|
} __attribute__((packed));
|
|
|
|
/*
|
|
* Get the return address for a single stackframe and return a pointer to the
|
|
* next frame tail.
|
|
*/
|
|
static struct frame_tail __user *
|
|
user_backtrace(struct frame_tail __user *tail,
|
|
struct perf_callchain_entry *entry)
|
|
{
|
|
struct frame_tail buftail;
|
|
|
|
/* Also check accessibility of one struct frame_tail beyond */
|
|
if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
|
|
return NULL;
|
|
if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
|
|
return NULL;
|
|
|
|
perf_callchain_store(entry, buftail.lr);
|
|
|
|
/*
|
|
* Frame pointers should strictly progress back up the stack
|
|
* (towards higher addresses).
|
|
*/
|
|
if (tail + 1 >= buftail.fp)
|
|
return NULL;
|
|
|
|
return buftail.fp - 1;
|
|
}
|
|
|
|
void
|
|
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
|
|
{
|
|
struct frame_tail __user *tail;
|
|
|
|
|
|
tail = (struct frame_tail __user *)regs->ARM_fp - 1;
|
|
|
|
while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
|
|
tail && !((unsigned long)tail & 0x3))
|
|
tail = user_backtrace(tail, entry);
|
|
}
|
|
|
|
/*
|
|
* Gets called by walk_stackframe() for every stackframe. This will be called
|
|
* whist unwinding the stackframe and is like a subroutine return so we use
|
|
* the PC.
|
|
*/
|
|
static int
|
|
callchain_trace(struct stackframe *fr,
|
|
void *data)
|
|
{
|
|
struct perf_callchain_entry *entry = data;
|
|
perf_callchain_store(entry, fr->pc);
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
|
|
{
|
|
struct stackframe fr;
|
|
|
|
fr.fp = regs->ARM_fp;
|
|
fr.sp = regs->ARM_sp;
|
|
fr.lr = regs->ARM_lr;
|
|
fr.pc = regs->ARM_pc;
|
|
walk_stackframe(&fr, callchain_trace, entry);
|
|
}
|