mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 13:13:57 +08:00
b9b37787d2
Because the VIA SuperIO chip only decodes 24 bits of address space but port address space currently being configured as 32MB there is the theoretical possibility of aliases within the I/O port address range. The complicated solution is to reserve all address range that potencially could cause such aliases. But with the PCI spec limiting port allocations for devices to a maximum of 256 bytes 16MB of port address space already is way more than one would ever expect to be used so we just reduce the port space to 16MB. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> To: Yoichi Yuasa <yuasa@linux-mips.org> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: linux-mips@linux-mips.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Patchwork: http://patchwork.linux-mips.org/patch/995/
49 lines
1.2 KiB
C
49 lines
1.2 KiB
C
/*
|
|
* Register PCI controller.
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
|
|
* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
|
|
*
|
|
*/
|
|
#include <linux/init.h>
|
|
#include <linux/pci.h>
|
|
|
|
#include <asm/gt64120.h>
|
|
|
|
extern struct pci_ops gt64xxx_pci0_ops;
|
|
|
|
static struct resource cobalt_mem_resource = {
|
|
.start = GT_DEF_PCI0_MEM0_BASE,
|
|
.end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
|
|
.name = "PCI memory",
|
|
.flags = IORESOURCE_MEM,
|
|
};
|
|
|
|
static struct resource cobalt_io_resource = {
|
|
.start = 0x1000,
|
|
.end = 0xffffffUL,
|
|
.name = "PCI I/O",
|
|
.flags = IORESOURCE_IO,
|
|
};
|
|
|
|
static struct pci_controller cobalt_pci_controller = {
|
|
.pci_ops = >64xxx_pci0_ops,
|
|
.mem_resource = &cobalt_mem_resource,
|
|
.io_resource = &cobalt_io_resource,
|
|
.io_offset = 0 - GT_DEF_PCI0_IO_BASE,
|
|
.io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
|
|
};
|
|
|
|
static int __init cobalt_pci_init(void)
|
|
{
|
|
register_pci_controller(&cobalt_pci_controller);
|
|
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(cobalt_pci_init);
|