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58dcfb3a0f
USBTLL Save-and-Restore is broken in 3630 ES1.0. Having it enabled could result in incorrect register restores as the OMAP exits off-mode. This could potentially result in unexpected wakeup events. (Refer 3630 errata ID i579) This is fixed in ES1.1. So disable it for ES1.0s. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
260 lines
6.5 KiB
C
260 lines
6.5 KiB
C
/*
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* OMAP3 powerdomain definitions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Written by Paul Walmsley
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* Debugging and integration fixes by Jouni Högander
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
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#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
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/*
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* N.B. If powerdomains are added or removed from this file, update
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* the array in mach-omap2/powerdomains.h.
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*/
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#include <plat/powerdomain.h>
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#include "prcm-common.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/*
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* 34XX-specific powerdomains, dependencies
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*/
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#ifdef CONFIG_ARCH_OMAP3
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/*
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* Powerdomains
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*/
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static struct powerdomain iva2_pwrdm = {
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.name = "iva2_pwrdm",
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.prcm_offs = OMAP3430_IVA2_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 4,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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[1] = PWRSTS_OFF_RET,
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[2] = PWRSTS_OFF_RET,
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[3] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON,
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[1] = PWRDM_POWER_ON,
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[2] = PWRSTS_OFF_ON,
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[3] = PWRDM_POWER_ON,
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},
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};
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static struct powerdomain mpu_3xxx_pwrdm = {
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.name = "mpu_pwrdm",
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.prcm_offs = MPU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_MPU_QUIRK,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_ON,
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},
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};
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/*
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* The USBTLL Save-and-Restore mechanism is broken on
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* 3430s upto ES3.0 and 3630ES1.0. Hence this feature
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* needs to be disabled on these chips.
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* Refer: 3430 errata ID i459 and 3630 errata ID i579
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*/
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static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
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CHIP_IS_OMAP3430ES2 |
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CHIP_IS_OMAP3430ES3_0 |
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CHIP_IS_OMAP3630ES1),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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};
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static struct powerdomain core_3xxx_es3_1_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
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CHIP_GE_OMAP3630ES1_1),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
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},
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};
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static struct powerdomain dss_pwrdm = {
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.name = "dss_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.prcm_offs = OMAP3430_DSS_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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/*
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* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
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* possible SGX powerstate, the SGX device itself does not support
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* retention.
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*/
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static struct powerdomain sgx_pwrdm = {
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.name = "sgx_pwrdm",
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.prcm_offs = OMAP3430ES2_SGX_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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/* XXX This is accurate for 3430 SGX, but what about GFX? */
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.pwrsts = PWRSTS_OFF_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain cam_pwrdm = {
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.name = "cam_pwrdm",
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.prcm_offs = OMAP3430_CAM_MOD,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain per_pwrdm = {
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.name = "per_pwrdm",
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.prcm_offs = OMAP3430_PER_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain emu_pwrdm = {
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.name = "emu_pwrdm",
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.prcm_offs = OMAP3430_EMU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain neon_pwrdm = {
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.name = "neon_pwrdm",
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.prcm_offs = OMAP3430_NEON_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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};
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static struct powerdomain usbhost_pwrdm = {
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.name = "usbhost_pwrdm",
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.prcm_offs = OMAP3430ES2_USBHOST_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_RET,
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/*
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* REVISIT: Enabling usb host save and restore mechanism seems to
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* leave the usb host domain permanently in ACTIVE mode after
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* changing the usb host power domain state from OFF to active once.
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* Disabling for now.
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*/
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/*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* MEMONSTATE */
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},
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};
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static struct powerdomain dpll1_pwrdm = {
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.name = "dpll1_pwrdm",
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.prcm_offs = MPU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain dpll2_pwrdm = {
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.name = "dpll2_pwrdm",
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.prcm_offs = OMAP3430_IVA2_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain dpll3_pwrdm = {
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.name = "dpll3_pwrdm",
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.prcm_offs = PLL_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain dpll4_pwrdm = {
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.name = "dpll4_pwrdm",
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.prcm_offs = PLL_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct powerdomain dpll5_pwrdm = {
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.name = "dpll5_pwrdm",
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.prcm_offs = PLL_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
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};
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#endif /* CONFIG_ARCH_OMAP3 */
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#endif
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