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44169075e6
This patch adds the support for OMAP4. The platform and machine specific headers and sources updated for OMAP4430 SDP platform. OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
135 lines
4.8 KiB
C
135 lines
4.8 KiB
C
/*
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* Common io.c file
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* This file is created by Russell King <rmk+kernel@arm.linux.org.uk>
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <mach/omap730.h>
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#include <mach/omap1510.h>
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#include <mach/omap16xx.h>
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#include <mach/omap24xx.h>
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#include <mach/omap34xx.h>
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#include <mach/omap44xx.h>
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#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
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#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
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/*
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* Intercept ioremap() requests for addresses in our fixed mapping regions.
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*/
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void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
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{
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#ifdef CONFIG_ARCH_OMAP1
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if (cpu_class_is_omap1()) {
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if (BETWEEN(p, IO_PHYS, IO_SIZE))
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return XLATE(p, IO_PHYS, IO_VIRT);
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}
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if (cpu_is_omap730()) {
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if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
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return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
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if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
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return XLATE(p, OMAP730_DSPREG_BASE,
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OMAP730_DSPREG_START);
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}
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if (cpu_is_omap15xx()) {
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if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
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return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START);
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if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE))
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return XLATE(p, OMAP1510_DSPREG_BASE,
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OMAP1510_DSPREG_START);
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}
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if (cpu_is_omap16xx()) {
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if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE))
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return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START);
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if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE))
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return XLATE(p, OMAP16XX_DSPREG_BASE,
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OMAP16XX_DSPREG_START);
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP2
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if (cpu_is_omap24xx()) {
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if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
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return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
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if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
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return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
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}
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if (cpu_is_omap2420()) {
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if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
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return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
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if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
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return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE);
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if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
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return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
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}
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if (cpu_is_omap2430()) {
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if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
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return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
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if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
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return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
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if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
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return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
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if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
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return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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if (cpu_is_omap34xx()) {
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if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
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return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
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if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
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return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
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if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
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return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
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if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
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return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
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if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
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return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
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if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
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return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
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if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
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return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
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if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
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return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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if (cpu_is_omap44xx()) {
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if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE))
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return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT);
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if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE))
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return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT);
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if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE))
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return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
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if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
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return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
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if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
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return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
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if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
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return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
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}
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#endif
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return __arm_ioremap(p, size, type);
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}
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EXPORT_SYMBOL(omap_ioremap);
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void omap_iounmap(volatile void __iomem *addr)
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{
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unsigned long virt = (unsigned long)addr;
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if (virt >= VMALLOC_START && virt < VMALLOC_END)
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__iounmap(addr);
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}
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EXPORT_SYMBOL(omap_iounmap);
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