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7a4fad480d
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs - Dhanajay enables pinctrl for the Northstar2 SoCs - Jon Mason enables all of the UART peripherals found in the NS2 SVK and finally adds the CCI-400 and PMU nodes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXY1QtAAoJEIfQlpxEBwcEOk4QAObsEiL/mCR0mx/6+QC0kivU LRrfHKKkMOjpvGZaY9I19CW3toWZB5Nr7B8FtsEQf/Nwp35ug4e0ajPw52DGuvyU 1xhWHwQ7rIPP9FU3/1wHZ1Na26m9GeN1RAr7ljHCymOaK0yyFNWvP6GQs1ZyYZsf kc4NjRU4gckNi5ouYtdPM5DtU1OGeXk4jesX8PEZJ/C4DxhIpIod6pgZRmxxw6p8 6MLra/ZccNHsSUoc0OV66GYLc02TRNGejB9vIVNl6QyoNabsEWRXMNEdM0Zn9i80 nF8kZvwYS1333wS1p5RilwFMOfE2qF0MzYFnwDgOqdk0D7ugoEE/Y1lYolce2u1p rTdf3y4QpRnRWAf+SwcGcJZE4XZ6kY19qBfvGv3kbRKnPTVMVME+w7vYQdGyPcMz jxgU1gaAqK/nHoCnOuh0GoP5PROlJOLXyC2ivRUehsnfg+0U6XU+jjtj9H5cnq20 ZQSv8uwqeppu7uPyh3BChrc1Zm78fUQRYcqOvtJkrttub+oeVN/tWIIkUu9t1m89 vBJe3zixuN/EghMn85sLimB+yEu7ETTujgvGtbp6Wp7ku5+7RbDJy+QlbdDZho8K JYfLq2kCW6KBrrIXyrvYrbTv/vys5bFaZ88XcHYNs657xVR+rxUov8O9jvNEqbxp qSrWCfaMyLqOV1VCrf5s =296G -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64 This pull request contains Device Tree changes for Broadcom ARM64-based SoCS: - Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs - Dhanajay enables pinctrl for the Northstar2 SoCs - Jon Mason enables all of the UART peripherals found in the NS2 SVK and finally adds the CCI-400 and PMU nodes * tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux: arm64: dts: NS2: Add CCI-400 PMU support arm64: dts: NS2: Add all of the UARTs arm64: dts: Enable GPIO for Broadcom NS2 SoC arm64: dts: enable pinctrl for Broadcom NS2 SoC arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2 dt-bindings: ata: add compatible string for iProc AHCI controller Signed-off-by: Olof Johansson <olof@lixom.net> |
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