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adb1af9803
* Add IDE_TFLAG_FS taskfile flag and set it for REQ_TYPE_FS requests.
* Convert ->{in,out}put_data methods to take command instead of request
as an argument. Then convert pre_task_out_intr(), task_end_request(),
task_error(), task_in_unexpected(), ide_pio_sector(), ide_pio_multi()
and ide_pio_datablock() in similar way.
* Rename task_end_request() to ide_finish_cmd().
There should be no functional changes caused by this patch.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
166 lines
4.1 KiB
C
166 lines
4.1 KiB
C
/*
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* Q40 I/O port IDE Driver
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*
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* (c) Richard Zidlicky
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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*
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/ide.h>
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/*
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* Bases of the IDE interfaces
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*/
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#define Q40IDE_NUM_HWIFS 2
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#define PCIDE_BASE1 0x1f0
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#define PCIDE_BASE2 0x170
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#define PCIDE_BASE3 0x1e8
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#define PCIDE_BASE4 0x168
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#define PCIDE_BASE5 0x1e0
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#define PCIDE_BASE6 0x160
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static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
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PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
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PCIDE_BASE6 */
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};
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static int q40ide_default_irq(unsigned long base)
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{
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switch (base) {
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case 0x1f0: return 14;
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case 0x170: return 15;
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case 0x1e8: return 11;
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default:
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return 0;
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}
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}
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/*
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* Addresses are pretranslated for Q40 ISA access.
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*/
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static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
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ide_ack_intr_t *ack_intr,
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int irq)
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{
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memset(hw, 0, sizeof(hw_regs_t));
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/* BIG FAT WARNING:
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assumption: only DATA port is ever used in 16 bit mode */
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hw->io_ports.data_addr = Q40_ISA_IO_W(base);
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hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
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hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
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hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
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hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
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hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
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hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
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hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
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hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
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hw->irq = irq;
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hw->ack_intr = ack_intr;
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hw->chipset = ide_generic;
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}
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static void q40ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
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void *buf, unsigned int len)
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{
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unsigned long data_addr = drive->hwif->io_ports.data_addr;
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if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS))
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return insw(data_addr, buf, (len + 1) / 2);
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raw_insw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
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}
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static void q40ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
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void *buf, unsigned int len)
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{
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unsigned long data_addr = drive->hwif->io_ports.data_addr;
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if (drive->media == ide_disk && cmd && (cmd->tf_flags & IDE_TFLAG_FS))
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return outsw(data_addr, buf, (len + 1) / 2);
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raw_outsw_swapw((u16 *)data_addr, buf, (len + 1) / 2);
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}
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/* Q40 has a byte-swapped IDE interface */
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static const struct ide_tp_ops q40ide_tp_ops = {
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.exec_command = ide_exec_command,
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.read_status = ide_read_status,
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.read_altstatus = ide_read_altstatus,
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.set_irq = ide_set_irq,
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.tf_load = ide_tf_load,
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.tf_read = ide_tf_read,
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.input_data = q40ide_input_data,
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.output_data = q40ide_output_data,
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};
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static const struct ide_port_info q40ide_port_info = {
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.tp_ops = &q40ide_tp_ops,
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.host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA,
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.irq_flags = IRQF_SHARED,
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};
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/*
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* the static array is needed to have the name reported in /proc/ioports,
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* hwif->name unfortunately isn't available yet
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*/
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static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
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"ide0", "ide1"
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};
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/*
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* Probe for Q40 IDE interfaces
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*/
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static int __init q40ide_init(void)
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{
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int i;
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hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
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if (!MACH_IS_Q40)
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return -ENODEV;
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printk(KERN_INFO "ide: Q40 IDE controller\n");
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for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
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const char *name = q40_ide_names[i];
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if (!request_region(pcide_bases[i], 8, name)) {
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printk("could not reserve ports %lx-%lx for %s\n",
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pcide_bases[i],pcide_bases[i]+8,name);
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continue;
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}
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if (!request_region(pcide_bases[i]+0x206, 1, name)) {
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printk("could not reserve port %lx for %s\n",
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pcide_bases[i]+0x206,name);
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release_region(pcide_bases[i], 8);
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continue;
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}
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q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
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q40ide_default_irq(pcide_bases[i]));
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hws[i] = &hw[i];
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}
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return ide_host_add(&q40ide_port_info, hws, NULL);
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}
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module_init(q40ide_init);
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MODULE_LICENSE("GPL");
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