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79e0899275
While looking into adding atomic-pwm support to the pwm-crc driver I noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and there is a clock-divider which divides this with a value between 1-128, and there are 256 duty-cycle steps. The pwm-crc code before this commit assumed that a clock-divider setting of 1 means that the PWM output is running at 6 MHZ, if that is true, where do these 256 duty-cycle steps come from? This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that seems unlikely for a PMIC which is using a silicon process optimized for power-switching transistors. It is way more likely that there is an 8 bit counter for the duty cycle which acts as an extra fixed divider wrt the PWM output frequency. The main user of the pwm-crc driver is the i915 GPU driver which uses it for backlight control. Lets compare the PWM register values set by the video-BIOS (the GOP), assuming the extra fixed divider is present versus the PWM frequency specified in the Video-BIOS-Tables: Device: PWM Hz set by BIOS PWM Hz specified in VBT Asus T100TA 200 200 Asus T100HA 200 200 Lenovo Miix 2 8 23437 20000 Toshiba WT8-A 23437 20000 So as we can see if we assume the extra division by 256 then the register values set by the GOP are an exact match for the VBT values, where as otherwise the values would be of by a factor of 256. This commit fixes the period / duty_cycle calculations to take the extra division by 256 into account. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200903112337.4113-9-hdegoede@redhat.com
136 lines
3.2 KiB
C
136 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Intel Corporation. All rights reserved.
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*
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* Author: Shobhit Kumar <shobhit.kumar@intel.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/pwm.h>
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#define PWM0_CLK_DIV 0x4B
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#define PWM_OUTPUT_ENABLE BIT(7)
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#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
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#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
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#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
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#define PWM0_DUTY_CYCLE 0x4E
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#define BACKLIGHT_EN 0x51
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#define PWM_MAX_LEVEL 0xFF
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#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */
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#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */
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/**
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* struct crystalcove_pwm - Crystal Cove PWM controller
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* @chip: the abstract pwm_chip structure.
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* @regmap: the regmap from the parent device.
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*/
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struct crystalcove_pwm {
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struct pwm_chip chip;
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struct regmap *regmap;
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};
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static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
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{
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return container_of(pc, struct crystalcove_pwm, chip);
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}
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static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
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return 0;
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}
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static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
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}
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static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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struct device *dev = crc_pwm->chip.dev;
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int level;
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if (period_ns > PWM_MAX_PERIOD_NS) {
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dev_err(dev, "un-supported period_ns\n");
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return -EINVAL;
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}
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if (pwm_get_period(pwm) != period_ns) {
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int clk_div;
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/* changing the clk divisor, need to disable fisrt */
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crc_pwm_disable(c, pwm);
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clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
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regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
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clk_div | PWM_OUTPUT_ENABLE);
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/* enable back */
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crc_pwm_enable(c, pwm);
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}
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/* change the pwm duty cycle */
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level = duty_ns * PWM_MAX_LEVEL / period_ns;
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regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
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return 0;
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}
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static const struct pwm_ops crc_pwm_ops = {
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.config = crc_pwm_config,
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.enable = crc_pwm_enable,
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.disable = crc_pwm_disable,
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};
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static int crystalcove_pwm_probe(struct platform_device *pdev)
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{
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struct crystalcove_pwm *pwm;
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struct device *dev = pdev->dev.parent;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &crc_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = 1;
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/* get the PMIC regmap */
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pwm->regmap = pmic->regmap;
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platform_set_drvdata(pdev, pwm);
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return pwmchip_add(&pwm->chip);
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}
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static int crystalcove_pwm_remove(struct platform_device *pdev)
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{
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struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);
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return pwmchip_remove(&pwm->chip);
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}
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static struct platform_driver crystalcove_pwm_driver = {
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.probe = crystalcove_pwm_probe,
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.remove = crystalcove_pwm_remove,
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.driver = {
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.name = "crystal_cove_pwm",
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},
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};
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builtin_platform_driver(crystalcove_pwm_driver);
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