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193c9d23a0
Align compatible strings for several IP blocks present on Tegra chips with the latest doctrine from the DT maintainers: http://marc.info/?l=devicetree&m=142255654213019&w=2 The primary objective here is to avoid checkpatch warnings, per: http://marc.info/?l=linux-tegra&m=142201349727836&w=2 DT binding text files have been updated for the following IP blocks: - PCIe - SOR - SoC timers - AHB "gizmo" - APB_MISC - pinmux control - UART - PWM - I2C - SPI - RTC - PMC - eFuse - AHCI - HDA - XUSB_PADCTRL - SDHCI - SOC_THERM - AHUB - I2S - EHCI - USB PHY N.B. The nvidia,tegra20-timer compatible string is removed from the nvidia,tegra30-timer.txt documentation file because it's already mentioned in the nvidia,tegra20-timer.txt documentation file. This second version takes into account the following requests from Rob Herring <robherring2@gmail.com>: - Per-IP block patches have been combined into a single patch - Explicit documentation about which compatible strings are actually matched by the driver has been removed. In its place is implicit documentation that loosely follows Rob's prescribed format: "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ..." [...] "You should attempt to document known values of <chip> if you use it" Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Dylan Reid <dgreid@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jingchang Lu <jingchang.lu@freescale.com> Cc: John Crispin <blogic@openwrt.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mikko Perttunen <mperttunen@nvidia.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Takashi Iwai <tiwai@suse.de> Cc: Tejun Heo <tj@kernel.org> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Zhang Rui <rui.zhang@intel.com> Cc: dri-devel@lists.freedesktop.org Cc: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-pwm@vger.kernel.org Cc: linux-tegra@vger.kernel.org Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
379 lines
13 KiB
Plaintext
379 lines
13 KiB
Plaintext
NVIDIA Tegra host1x
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Required properties:
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- compatible: "nvidia,tegra<chip>-host1x"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- #address-cells: The number of cells used to represent physical base addresses
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in the host1x address space. Should be 1.
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- #size-cells: The number of cells used to represent the size of an address
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range in the host1x address space. Should be 1.
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- ranges: The mapping of the host1x address space to the CPU address space.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- host1x
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The host1x top-level node defines a number of children, each representing one
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of the following host1x client modules:
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- mpe: video encoder
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Required properties:
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- compatible: "nvidia,tegra<chip>-mpe"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- mpe
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- vi: video input
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Required properties:
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- compatible: "nvidia,tegra<chip>-vi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- vi
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- epp: encoder pre-processor
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Required properties:
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- compatible: "nvidia,tegra<chip>-epp"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- epp
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- isp: image signal processor
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Required properties:
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- compatible: "nvidia,tegra<chip>-isp"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- isp
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- gr2d: 2D graphics engine
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Required properties:
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- compatible: "nvidia,tegra<chip>-gr2d"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- 2d
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- gr3d: 3D graphics engine
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Required properties:
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- compatible: "nvidia,tegra<chip>-gr3d"
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- reg: Physical base address and length of the controller's registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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(This property may be omitted if the only clock in the list is "3d")
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- 3d
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This MUST be the first entry.
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- 3d2 (Only required on SoCs with two 3D clocks)
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- 3d
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- 3d2 (Only required on SoCs with two 3D clocks)
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- dc: display controller
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Required properties:
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- compatible: "nvidia,tegra<chip>-dc"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- dc
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This MUST be the first entry.
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- parent
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- dc
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- nvidia,head: The number of the display controller head. This is used to
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setup the various types of output to receive video data from the given
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head.
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Each display controller node has a child node, named "rgb", that represents
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the RGB output associated with the controller. It can take the following
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optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- nvidia,panel: phandle of a display panel
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- hdmi: High Definition Multimedia Interface
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Required properties:
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- compatible: "nvidia,tegra<chip>-hdmi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- hdmi-supply: supply for the +5V HDMI connector pin
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- vdd-supply: regulator for supply voltage
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- pll-supply: regulator for PLL
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- hdmi
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This MUST be the first entry.
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- parent
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- hdmi
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Optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- nvidia,panel: phandle of a display panel
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- tvo: TV encoder output
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Required properties:
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- compatible: "nvidia,tegra<chip>-tvo"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- dsi: display serial interface
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Required properties:
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- compatible: "nvidia,tegra<chip>-dsi"
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- reg: Physical base address and length of the controller's registers.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- dsi
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This MUST be the first entry.
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- lp
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- parent
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- dsi
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- avdd-dsi-supply: phandle of a supply that powers the DSI controller
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- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
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which pads are used by this DSI output and need to be calibrated. See also
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../mipi/nvidia,tegra114-mipi.txt.
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Optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- nvidia,panel: phandle of a display panel
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- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
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up with in order to support up to 8 data lanes
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- sor: serial output resource
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Required properties:
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- compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
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must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
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is tegra132.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- sor: clock input for the SOR hardware
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- parent: input for the pixel clock
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- dp: reference clock for the SOR clock
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- safe: safe reference for the SOR clock during power up
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- sor
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Optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- nvidia,panel: phandle of a display panel
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Optional properties when driving an eDP output:
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- nvidia,dpaux: phandle to a DispayPort AUX interface
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- dpaux: DisplayPort AUX interface
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- compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
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must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
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<chip> is tegra132.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- dpaux: clock input for the DPAUX hardware
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- parent: reference clock
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- dpaux
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- vdd-supply: phandle of a supply that powers the DisplayPort link
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Example:
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/ {
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...
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host1x {
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compatible = "nvidia,tegra20-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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interrupts = <0 65 0x04 /* mpcore syncpt */
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0 67 0x04>; /* mpcore general */
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clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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mpe {
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compatible = "nvidia,tegra20-mpe";
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reg = <0x54040000 0x00040000>;
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interrupts = <0 68 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_MPE>;
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resets = <&tegra_car 60>;
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reset-names = "mpe";
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};
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vi {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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resets = <&tegra_car 100>;
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reset-names = "vi";
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};
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epp {
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compatible = "nvidia,tegra20-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <0 70 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_EPP>;
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resets = <&tegra_car 19>;
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reset-names = "epp";
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};
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isp {
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compatible = "nvidia,tegra20-isp";
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reg = <0x54100000 0x00040000>;
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interrupts = <0 71 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_ISP>;
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resets = <&tegra_car 23>;
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reset-names = "isp";
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};
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gr2d {
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compatible = "nvidia,tegra20-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <0 72 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_GR2D>;
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resets = <&tegra_car 21>;
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reset-names = "2d";
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};
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gr3d {
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compatible = "nvidia,tegra20-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car TEGRA20_CLK_GR3D>;
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resets = <&tegra_car 24>;
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reset-names = "3d";
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};
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dc@54200000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <0 73 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_DISP1>,
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<&tegra_car TEGRA20_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <0 74 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_DISP2>,
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<&tegra_car TEGRA20_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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rgb {
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status = "disabled";
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};
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};
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hdmi {
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compatible = "nvidia,tegra20-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <0 75 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_HDMI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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status = "disabled";
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};
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tvo {
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compatible = "nvidia,tegra20-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <0 76 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_TVO>;
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status = "disabled";
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};
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dsi {
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compatible = "nvidia,tegra20-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car TEGRA20_CLK_DSI>,
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<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "parent";
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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status = "disabled";
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};
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};
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...
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};
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