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dd821823fa
Invalidating outer cache without disabling it is a big nono, and so, remove the machine specific outer.inv_all And at the same time it does not prevent us overriding outer.disable as we do not have any such secure SMI to handle the same while kexec disables the outer cache. Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2011
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/hardware.h>
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#include <mach/id.h>
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static void __iomem *l2x0_base;
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static int __init ux500_l2x0_unlock(void)
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{
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int i;
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/*
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* Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
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* apparently locks both caches before jumping to the kernel. The
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* l2x0 core will not touch the unlock registers if the l2x0 is
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* already enabled, so we do it right here instead. The PL310 has
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* 8 sets of registers, one per possible CPU.
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*/
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for (i = 0; i < 8; i++) {
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
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i * L2X0_LOCKDOWN_STRIDE);
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}
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return 0;
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}
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static int __init ux500_l2x0_init(void)
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{
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if (cpu_is_u5500())
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l2x0_base = __io_address(U5500_L2CC_BASE);
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else if (cpu_is_u8500())
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l2x0_base = __io_address(U8500_L2CC_BASE);
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else
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ux500_unknown_soc();
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/* Unlock before init */
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ux500_l2x0_unlock();
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/* 64KB way size, 8 way associativity, force WA */
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l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
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/*
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* We can't disable l2 as we are in non secure mode, currently
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* this seems be called only during kexec path. So let's
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* override outer.disable with nasty assignment until we have
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* some SMI service available.
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*/
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outer_cache.disable = NULL;
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return 0;
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}
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early_initcall(ux500_l2x0_init);
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