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830145796a
The arch/arm/mach-exynos4 directory (CONFIG_ARCH_EXYNOS4) has made for plaforms based on EXYNOS4 SoCs. But since upcoming Samsung's SoCs such as EXYNOS5 (ARM Cortex A15) can reuse most codes in current mach-exynos4, one mach-exynos directory will be used for them. This patch changes to CONFIG_ARCH_EXYNOS (arch/arm/mach-exynos) but keeps original CONFIG_ARCH_EXYNOS4 in mach-exynos/Kconfig to avoid changing in driver side. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
/*
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* linux/arch/arm/mach-exynos4/clock-exynos4212.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4212 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/exynos4.h>
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#include <plat/pm.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/exynos4-clock.h>
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static struct sleep_save exynos4212_clock_save[] = {
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SAVE_ITEM(S5P_CLKSRC_IMAGE),
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SAVE_ITEM(S5P_CLKDIV_IMAGE),
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SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
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SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
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};
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static struct clk *clk_src_mpll_user_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &clk_mout_mpll.clk,
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};
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static struct clksrc_sources clk_src_mpll_user = {
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.sources = clk_src_mpll_user_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
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};
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static struct clksrc_clk clk_mout_mpll_user = {
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.clk = {
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.name = "mout_mpll_user",
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},
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.sources = &clk_src_mpll_user,
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.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
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};
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_mpll_user,
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};
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static struct clksrc_clk clksrcs[] = {
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/* nothing here yet */
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};
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static struct clk init_clocks_off[] = {
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/* nothing here yet */
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};
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#ifdef CONFIG_PM_SLEEP
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static int exynos4212_clock_suspend(void)
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{
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s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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return 0;
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}
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static void exynos4212_clock_resume(void)
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{
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s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
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}
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#else
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#define exynos4212_clock_suspend NULL
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#define exynos4212_clock_resume NULL
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#endif
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struct syscore_ops exynos4212_clock_syscore_ops = {
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.suspend = exynos4212_clock_suspend,
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.resume = exynos4212_clock_resume,
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};
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void __init exynos4212_register_clocks(void)
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{
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int ptr;
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/* usbphy1 is removed */
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clkset_group_list[4] = NULL;
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/* mout_mpll_user is used */
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clkset_group_list[6] = &clk_mout_mpll_user.clk;
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clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
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clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
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clk_mout_mpll.reg_src.shift = 12;
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clk_mout_mpll.reg_src.size = 1;
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for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
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s3c_register_clksrc(sysclks[ptr], 1);
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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register_syscore_ops(&exynos4212_clock_syscore_ops);
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}
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