Tomi Valkeinen 77ccbfbb07 OMAPDSS: DSI: Add code to disable PHY DCC ... OMAP5 DSI PHY has DCC (Duty Cycle Corrector) block, and by default DCC is enabled and thus the PLL clock is divided by 2 to get the DSI DDR clk. This divider has been 4 for all previous OMAPs, and changing it needs some reorganization of the code. The DCC can be disabled, and in that case the divider is back to the old 4. This patch adds dss feature for the DCC, and adds code to always disable the DCC. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>		2012-09-24 16:50:10 +03:00
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displays	OMAPDSS: TFP410: use devm_gpio_request_one	2012-09-07 20:02:09 +03:00
dss	OMAPDSS: DSI: Add code to disable PHY DCC	2012-09-24 16:50:10 +03:00
omapfb	OMAPFB: Clear framebuffers before they are registered	2012-09-11 13:51:28 +03:00
Kconfig	OMAP: DSS2: Add generic and Sharp panel drivers	2009-12-09 18:19:42 +02:00
Makefile	OMAP2: avoid descending into disabled framebuffer dirs	2011-05-11 14:20:53 +03:00
vram.c	OMAPDSS: VRAM: Remove clearing with sDMA	2012-09-07 20:02:09 +03:00
vrfb.c	OMAPDSS: VRFB: remove compiler warnings when CONFIG_BUG=n	2012-05-22 10:59:15 +03:00