mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 05:04:00 +08:00
4ff40d140e
The hws field of sun8i_v3s_hw_clks has only 74 members. However, the number specified by CLK_NUMBER is 77 (= CLK_I2S0 + 1). This leads to runtime segmentation fault that is not always reproducible. This patch fixes the problem by specifying correct clock number. Signed-off-by: Yunhao Tian <18373444@buaa.edu.cn> [Maxime: Also remove the CLK_NUMBER definition] Signed-off-by: Maxime Ripard <maxime@cerno.tech>
55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
/*
|
|
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
|
|
*
|
|
* Based on ccu-sun8i-h3.h, which is:
|
|
* Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
*/
|
|
|
|
#ifndef _CCU_SUN8I_H3_H_
|
|
#define _CCU_SUN8I_H3_H_
|
|
|
|
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
|
|
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
|
|
|
|
#define CLK_PLL_CPU 0
|
|
#define CLK_PLL_AUDIO_BASE 1
|
|
#define CLK_PLL_AUDIO 2
|
|
#define CLK_PLL_AUDIO_2X 3
|
|
#define CLK_PLL_AUDIO_4X 4
|
|
#define CLK_PLL_AUDIO_8X 5
|
|
#define CLK_PLL_VIDEO 6
|
|
#define CLK_PLL_VE 7
|
|
#define CLK_PLL_DDR0 8
|
|
#define CLK_PLL_PERIPH0 9
|
|
#define CLK_PLL_PERIPH0_2X 10
|
|
#define CLK_PLL_ISP 11
|
|
#define CLK_PLL_PERIPH1 12
|
|
/* Reserve one number for not implemented and not used PLL_DDR1 */
|
|
|
|
/* The CPU clock is exported */
|
|
|
|
#define CLK_AXI 15
|
|
#define CLK_AHB1 16
|
|
#define CLK_APB1 17
|
|
#define CLK_APB2 18
|
|
#define CLK_AHB2 19
|
|
|
|
/* All the bus gates are exported */
|
|
|
|
/* The first bunch of module clocks are exported */
|
|
|
|
#define CLK_DRAM 58
|
|
|
|
/* All the DRAM gates are exported */
|
|
|
|
/* Some more module clocks are exported */
|
|
|
|
#define CLK_MBUS 72
|
|
|
|
/* And the GPU module clock is exported */
|
|
|
|
#define CLK_PLL_DDR1 74
|
|
|
|
#endif /* _CCU_SUN8I_H3_H_ */
|