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abf12d719a
Dynamically detect the DBx500 SOC an revision based on the ASIC ID. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include <asm/localtimer.h>
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#include <plat/mtu.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include <mach/devices.h>
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#include <mach/prcmu.h>
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#include "clock.h"
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#ifdef CONFIG_CACHE_L2X0
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static void __iomem *l2x0_base;
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#endif
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void __init ux500_init_irq(void)
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{
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void __iomem *dist_base;
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void __iomem *cpu_base;
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if (cpu_is_u5500()) {
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dist_base = __io_address(U5500_GIC_DIST_BASE);
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cpu_base = __io_address(U5500_GIC_CPU_BASE);
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} else if (cpu_is_u8500()) {
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dist_base = __io_address(U8500_GIC_DIST_BASE);
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cpu_base = __io_address(U8500_GIC_CPU_BASE);
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} else
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ux500_unknown_soc();
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gic_init(0, 29, dist_base, cpu_base);
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/*
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* Init clocks here so that they are available for system timer
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* initialization.
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*/
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if (cpu_is_u8500())
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prcmu_early_init();
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clk_init();
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}
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#ifdef CONFIG_CACHE_L2X0
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static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* wait for the operation to complete */
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while (readl_relaxed(reg) & mask)
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;
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}
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static inline void ux500_cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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writel_relaxed(0, base + L2X0_CACHE_SYNC);
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ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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/*
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* The L2 cache cannot be turned off in the non-secure world.
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* Dummy until a secure service is in place.
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*/
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static void ux500_l2x0_disable(void)
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{
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}
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/*
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* This is only called when doing a kexec, just after turning off the L2
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* and L1 cache, and it is surrounded by a spinlock in the generic version.
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* However, we're not really turning off the L2 cache right now and the
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* PL310 does not support exclusive accesses (used to implement the spinlock).
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* So, the invalidation needs to be done without the spinlock.
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*/
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static void ux500_l2x0_inv_all(void)
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{
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void __iomem *base = l2x0_base;
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uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
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/* invalidate all ways */
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writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
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ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
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ux500_cache_sync();
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}
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static int ux500_l2x0_init(void)
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{
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if (cpu_is_u5500())
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l2x0_base = __io_address(U5500_L2CC_BASE);
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else if (cpu_is_u8500())
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l2x0_base = __io_address(U8500_L2CC_BASE);
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else
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ux500_unknown_soc();
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/* 64KB way size, 8 way associativity, force WA */
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l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
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/* Override invalidate function */
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outer_cache.disable = ux500_l2x0_disable;
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outer_cache.inv_all = ux500_l2x0_inv_all;
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return 0;
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}
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early_initcall(ux500_l2x0_init);
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#endif
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static void __init ux500_timer_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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/* Setup the local timer base */
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if (cpu_is_u5500())
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twd_base = __io_address(U5500_TWD_BASE);
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else if (cpu_is_u8500())
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twd_base = __io_address(U8500_TWD_BASE);
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else
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ux500_unknown_soc();
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#endif
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if (cpu_is_u5500())
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mtu_base = __io_address(U5500_MTU0_BASE);
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else if (cpu_is_u8500ed())
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mtu_base = __io_address(U8500_MTU0_BASE_ED);
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else if (cpu_is_u8500())
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mtu_base = __io_address(U8500_MTU0_BASE);
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else
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ux500_unknown_soc();
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nmdk_timer_init();
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}
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struct sys_timer ux500_timer = {
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.init = ux500_timer_init,
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};
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