mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 22:24:09 +08:00
886bc5ceb5
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*
|
|
* Synopsys Designware PCIe host controller driver
|
|
*
|
|
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* Author: Jingoo Han <jg1.han@samsung.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef _PCIE_DESIGNWARE_H
|
|
#define _PCIE_DESIGNWARE_H
|
|
|
|
/*
|
|
* Maximum number of MSI IRQs can be 256 per controller. But keep
|
|
* it 32 as of now. Probably we will never need more than 32. If needed,
|
|
* then increment it in multiple of 32.
|
|
*/
|
|
#define MAX_MSI_IRQS 32
|
|
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
|
|
|
|
/* Parameters for the waiting for link up routine */
|
|
#define LINK_WAIT_MAX_RETRIES 10
|
|
#define LINK_WAIT_USLEEP_MIN 90000
|
|
#define LINK_WAIT_USLEEP_MAX 100000
|
|
|
|
struct pcie_port {
|
|
struct device *dev;
|
|
u8 root_bus_nr;
|
|
void __iomem *dbi_base;
|
|
u64 cfg0_base;
|
|
void __iomem *va_cfg0_base;
|
|
u32 cfg0_size;
|
|
u64 cfg1_base;
|
|
void __iomem *va_cfg1_base;
|
|
u32 cfg1_size;
|
|
resource_size_t io_base;
|
|
phys_addr_t io_bus_addr;
|
|
u32 io_size;
|
|
u64 mem_base;
|
|
phys_addr_t mem_bus_addr;
|
|
u32 mem_size;
|
|
struct resource *cfg;
|
|
struct resource *io;
|
|
struct resource *mem;
|
|
struct resource *busn;
|
|
int irq;
|
|
u32 lanes;
|
|
struct pcie_host_ops *ops;
|
|
int msi_irq;
|
|
struct irq_domain *irq_domain;
|
|
unsigned long msi_data;
|
|
DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
|
|
};
|
|
|
|
struct pcie_host_ops {
|
|
void (*readl_rc)(struct pcie_port *pp,
|
|
void __iomem *dbi_base, u32 *val);
|
|
void (*writel_rc)(struct pcie_port *pp,
|
|
u32 val, void __iomem *dbi_base);
|
|
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
|
|
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
|
|
int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
|
|
unsigned int devfn, int where, int size, u32 *val);
|
|
int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
|
|
unsigned int devfn, int where, int size, u32 val);
|
|
int (*link_up)(struct pcie_port *pp);
|
|
void (*host_init)(struct pcie_port *pp);
|
|
void (*msi_set_irq)(struct pcie_port *pp, int irq);
|
|
void (*msi_clear_irq)(struct pcie_port *pp, int irq);
|
|
phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
|
|
u32 (*get_msi_data)(struct pcie_port *pp, int pos);
|
|
void (*scan_bus)(struct pcie_port *pp);
|
|
int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
|
|
};
|
|
|
|
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
|
|
int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
|
|
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
|
|
void dw_pcie_msi_init(struct pcie_port *pp);
|
|
int dw_pcie_wait_for_link(struct pcie_port *pp);
|
|
int dw_pcie_link_up(struct pcie_port *pp);
|
|
void dw_pcie_setup_rc(struct pcie_port *pp);
|
|
int dw_pcie_host_init(struct pcie_port *pp);
|
|
|
|
#endif /* _PCIE_DESIGNWARE_H */
|