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4683893574
Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module Standby and Software Reset support code, using the CPG/MSSR driver core. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/*
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* R-Car Gen2 Clock Pulse Generator
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN2_CPG_H__
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enum rcar_gen2_clk_types {
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CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN2_PLL0,
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CLK_TYPE_GEN2_PLL1,
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CLK_TYPE_GEN2_PLL3,
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CLK_TYPE_GEN2_Z,
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CLK_TYPE_GEN2_LB,
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CLK_TYPE_GEN2_ADSP,
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CLK_TYPE_GEN2_SDH,
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CLK_TYPE_GEN2_SD0,
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CLK_TYPE_GEN2_SD1,
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CLK_TYPE_GEN2_QSPI,
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CLK_TYPE_GEN2_RCAN,
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};
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struct rcar_gen2_cpg_pll_config {
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unsigned int extal_div;
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unsigned int pll1_mult;
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unsigned int pll3_mult;
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unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
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};
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struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core,
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const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base);
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int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
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unsigned int pll0_div, u32 mode);
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#endif
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